Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation

Abstract

The methodological approach of hammering multiple rows is newly proposed to evaluate today's SDRAMs, employed with in-DRAM mitigation circuits. The multiple rows are selected based on the one-row hammering test (single row hammering without refresh commands) and are exploited to defeat the employed mitigation algorithm. We irradiated the target sample using an X-ray to observe the reactions of the mitigation circuit when various combinations of multiple rows are hammered. The results showed a four times reduction in the number of hammering thresholds under the one-row hammering test. The same radiated sample showed no errors when one or a few rows were hammered due to the built-in mitigation circuit. However, multiple rows hammering (MRH) demonstrated its effectiveness by generating errors despite an active mitigation circuit. In this paper, we explore the X-ray damage results in the aging of the DRAM sample and induces vulnerabilities from the row hammering error perspective. Also, we use the error bits detected by MRH to investigate the coverage pitfalls of the mitigation circuit employed in the sample DRAM. Finally, we newly evaluate the remaining retention time under row hammering stress to explain the coverage loss in the mitigation strategy based solely on hammering counts.

Temperature Estimation of HBM2 Channels with Tail Distribution of Retention Errors in FPGA-HBM2 Platform

“…Dynamic retention errors were used in this study to determine the temperature sensitivity of DRAM cells. In the previous studies, retention errors were studied in a single DRAM cell [8,21] or a single DRAM device [22][23][24][25][26]. Because the retention errors in this study were measured using HBM2, the error information should contain the temperature information imposed by the HBM2 structure.…”