Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation

Li, M.; Bougard, Bruno; Catthoor, Francky

doi:10.1109/sips.2006.352548

Cited by 1 publication

(4 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, we can observe that the cycle-count measurement of the S-LMS is significantly lower than the optimized SRI-RLS. In the region [10,24] the difference is about a factor of 5. This strongly motivates multiple mode operation as an effective way to reduce average computation-load.…”

Section: Cycle-count and Memory-access Comparisonmentioning

confidence: 96%

“…On the contrary, the optimized SRI-RLS increases much slower, because the algorithmic exploration and redundancy removal significantly reduce the number of operations. In the region [10,24], the improvement of SRI-RLS cycle-count is around a factor of 8; when the length is larger than 40 the improvement is more than a factor of 10. In addition, we can observe that the cycle-count measurement of the S-LMS is significantly lower than the optimized SRI-RLS.…”

Section: Cycle-count and Memory-access Comparisonmentioning

confidence: 97%

“…However, the family of adaptive equalizer algorithms has countless members, even LMS itself has many variants, and many other advanced algorithms are also widely applied in practical equalizer implementations. For instance, the orthogonal-triangulardecomposition (QRD) based adaptive filter utilizing orthogonalization/projection principles are often applied to track fast fading channels [24,25].…”

Section: Variable Length Equalizermentioning

confidence: 99%

“…In this sub-section we introduce the controller that makes decision for algorithm switching. We proposed an efficient but effective solution based on feedback control with proportion-integral-difference (PID) algorithm [24,25]. The diagram of the algorithm switching scheme is depicted in Fig.…”

Section: Controller For Algorithm Switchingmentioning

confidence: 99%

See 3 more Smart Citations

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer

Bougard

Perre

et al. 2008

J Sign Process Syst Sign Image Video Technol

Self Cite

View full text Add to dashboard Cite

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.

show abstract

Section: Cycle-count and Memory-access Comparisonmentioning

confidence: 96%

Section: Cycle-count and Memory-access Comparisonmentioning

confidence: 97%

Section: Variable Length Equalizermentioning

confidence: 99%

Section: Controller For Algorithm Switchingmentioning

confidence: 99%

See 2 more Smart Citations