Explicit multi-threading (XMT) bridging models for instruction parallelism (extended abstract)

Vishkin, Uzi; Dascal, Shlomit; Berkovich, Efraim; Nuzman, Joseph

doi:10.1145/277651.277680

Cited by 39 publications

(30 citation statements)

References 14 publications

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“…Other examples include the Sun Niagara 2 [24] and the upcoming Intel Many Integrated Core (MIC) architecture. Research machines such as UT Austin's TRIPS [9], MIT's RAW [28] (available commercially as the TILE architecture from Tilera [2]), and UMD's XMT [33,36] are also examples of single-chip many-cores.…”

Section: Fig 1 Miss Handling Architecture (Mha) For a Banked Cache mentioning

confidence: 99%

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Caragea

Tzannes

Keceli

et al. 2011

Int J Parallel Prog

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Abstract. Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor numerous lighter cores with less resources, further reducing support for MLP on a per-core basis. Support for hardware and software prefetch increases MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15% in run-time on average across benchmarks and the state-of-the art GCC implementation by up to 34.79%, depending upon hardware configuration. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show run-time improvements of up to 24.61%. To demonstrate the robustness of our approach, we conduct a designspace exploration (DSE) for the considered target architecture by varying (i) the amount of chip resources designated for per-core prefetch storage and (ii) off-chip bandwidth. We show that the RAP algorithm is robust in that it improves performance across all design points considered. We also identify the Pareto-optimal hardware-software configuration which delivers 53.66% run-time improvement on average while using only 5.47% more chip area than the bare-bones design.

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Section: Fig 1 Miss Handling Architecture (Mha) For a Banked Cache mentioning

confidence: 99%

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Caragea

Tzannes

Keceli

et al. 2011

Int J Parallel Prog

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“…gives the von Neumann model, and with (p 1 ≥ 1, g 1 = ∞, L 1 = 0, m 1 ) gives the more general PRAM [16,27,40] model. In both instances m 1 is the size of the memory.…”

Section: The Multi-bsp Modelmentioning

confidence: 99%

A Bridging Model for Multi-core Computing

Valiant

2008

Algorithms - ESA 2008

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Writing software for one parallel system is a feasible though arduous task. Reusing the substantial intellectual effort so expended for programming a second system has proved much more challenging. In sequential computing algorithms textbooks and portable software are resources that enable software systems to be written that are efficiently portable across changing hardware platforms. These resources are currently lacking in the area of multi-core architectures, where a programmer seeking high performance has no comparable opportunity to build on the intellectual efforts of others.In order to address this problem we propose a bridging model aimed at capturing the most basic resource parameters of multi-core architectures. We suggest that the considerable intellectual effort needed for designing efficient algorithms for such architectures may be most fruitfully expended in designing portable algorithms, once and for all, for such a bridging model. Portable algorithms would contain efficient designs for all reasonable combinations of the basic resource parameters and input sizes, and would form the basis for implementation or compilation for particular machines.Our Multi-BSP model is a multi-level model that has explicit parameters for processor numbers, memory/cache sizes, communication costs, and synchronization costs. The lowest level corresponds to shared memory or the PRAM, acknowledging the relevance of that model for whatever limitations on memory and processor numbers it may be efficacious to emulate it.We propose parameter-aware portable algorithms that run efficiently on * This work was supported in part by NSF-CCF-04-27129. A preliminary version appeared in Proc. 16th Annual European Symposium on Algorithms, Sept 15-17, 2008, Karlsruhe Germany, LNCS Vol 5193, pp. 13-28, and had also been presented at SPAA, June [14][15][16] 2008.Email addresses: valiant@seas.harvard.edu (Leslie G. Valiant) January 15, 2010 all relevant architectures with any number of levels and any combination of parameters. For these algorithms we define a parameter-free notion of optimality. We show that for several fundamental problems, including standard matrix multiplication, the Fast Fourier Transform, and comparison sorting, there exist optimal portable algorithms in that sense, for all combinations of machine parameters. Thus some algorithmic generality and elegance can be found in this many parameter setting. Preprint submitted to Elsevier

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“…The SpawnMT model of [18] does not allow for nested initiation of an arbitrary-size spawn within a parallel spawn region. Such a feature, while useful, would be difficult to realize efficiently with hardware support.…”

Section: Xmt Programming Modelmentioning

confidence: 99%

“…Previous papers on XMT have discussed in detail its finegrained SPMD multi-threaded programming model, architectural support for concurrently executing multiple contexts on-chip, and preliminary evaluation of several parallel algorithms using hand-coded assembly programs [18] [7]. The introduction of an XMT compiler, presented here, allows us to evaluate XMT for the first time as a complete environment ("vertical prototyping"), using a much larger benchmark suite (with longer codes) than before.…”

Section: Introductionmentioning

confidence: 99%

Towards a First Vertical Prototyping of an Extremely Fine-Grained Parallel Programming Approach

Naishlos

Nuzman

Tseng

et al. 2003

Theory Comput Systems

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Explicit-multithreading (XMT) is a parallel programming approach for exploiting on-chip parallelism. XMT introduces a computational framework with 1) a simple programming style that relies on fine-grained PRAM-style algorithms; 2) hardware support for low-overhead parallel threads, scalable load balancing, and efficient synchronization. The missing link between the algorithmic-programming level and the architecture level is provided by the first prototype XMT compiler. This paper also takes this new opportunity to evaluate the overall effectiveness of the interaction between the programming model and the hardware, and enhance its performance where needed, incorporating new optimizations into the XMT compiler. We present a wide range of applications, which written in XMT obtain significant speedups relative to the best serial programs. We show that XMT is especially useful for more advanced applications with dynamic, irregular access pattern, where for regular computations we demonstrate performance gains that scale up to much higher levels than have been demonstrated before for on-chip systems.

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Explicit multi-threading (XMT) bridging models for instruction parallelism (extended abstract)

Cited by 39 publications

References 14 publications

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

A Bridging Model for Multi-core Computing

Towards a First Vertical Prototyping of an Extremely Fine-Grained Parallel Programming Approach

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