Experimental verification of the model for formation of double Shockley stacking faults in highly doped regions of PVT-grown 4H–SiC wafers

Abstract

We recently reported on the formation of overlapping rhombus-shaped stacking faults from scratches left over by the chemical mechanical polishing during high temperature annealing of PVT-grown 4H-SiC wafer. These stacking faults are restricted to regions with high N-doped areas of the wafer. The type of these stacking faults were determined

Glide of C-core partial dislocations along edges of expanding double-Shockley stacking faults in heavily nitrogen-doped 4H-SiC

“…The topography rules are that the pairs of Si-core PDs appear as bright contrast and the pairs of C-core PDs appear as dark contrast under the diffraction of = g 1128. [11][12][13] It has been suggested that the DSF formation is triggered by the mechanical damage on the crystal surface. 8,14,15) The first suggestive result for the relation between the damage and DSF nucleation was reported by Irmscher et al 13) After they annealed a heavily doped SiC crystal with local scratching on the surface, DSFs were found to have formed only in the damaged regions.…”

“…[11][12][13] It has been suggested that the DSF formation is triggered by the mechanical damage on the crystal surface. 8,14,15) The first suggestive result for the relation between the damage and DSF nucleation was reported by Irmscher et al 13) After they annealed a heavily doped SiC crystal with local scratching on the surface, DSFs were found to have formed only in the damaged regions. Hereby, they concluded that the DSF formation was initiated by PDs originating from surface damage.…”

“…15,16) In addition, it is known that the DSFs expand mainly though gliding of the Si-core PD pairs. [11][12][13]17) Although shear stress is often responsible for the dislocation glide on the slip plane, [18][19][20] the driving force relating to the localized electronic states around the faulted planes has been proposed for the DSF expansion.…”

Studies on Doping Concentration Variations in 4H-SiC Substrates Using X-ray Contour Mapping

“…It has been predicted theoretically that high nitrogen doping concentration level (above 2 x 10 19 cm -3 ) inside 4H-SiC crystal will increase propensity for formation of stacking faults [4]. The SFs inside can create quantum wells which can lower the free energy of the whole crystal once the barrier for partial dislocation motion is overcome by thermal energy (achieved by annealing above 1000 ⁰ C) [3][4]. Moreover, from a perspective of high power electronic applications, other severe issues, such as inhomogeneous resistivity and a large {0001} surface roughness of substrate are characteristic of heavily nitrogen doped SiC crystal [5].…”

Stacking Faults in 4H-SiC Single Crystal

“…碳化硅(SiC)是目前发展较为成熟的宽禁带半 导体材料之一, 具有宽带隙、高击穿电场、高饱和 电子漂移速度和高导热性等优异性能, 是制作高 温、高频、大功率和低损耗器件的优良材料 [1][2] 。目前, 已有多种 SiC 器件问世并逐步得到应用, 如 P-i-N 二 极管、肖特基二极管、MOSFET、光导开关 [3] 等。但 是, 目前 SiC 单晶材料仍然存在一些缺陷, 如微管、 多型、位错、堆垛层错等 [4][5][6][7] , 这在很大程度上限制 了 SiC 材料的应用 [8][9] 。微管作为碳化硅晶体的特有 缺陷, 经过行业多年深入研究, 已清楚其产生和演 变机理, 目前科锐(Cree)公司已能够提供零微管的 碳化硅衬底 [10] 。堆垛层错作为 SiC 晶体中的一种面 缺陷, 在 SiC 衬底外延过程中会繁衍到外延层中, 从而降低外延层的质量并影响最终 SiC 器件的性 能。Liu 等 [11] 对在 PVT 法生长过程中通氮气掺杂的 4H-SiC 晶片进行了研究, 在晶片中心区域观察到堆 垛层错, 他认为堆垛层错的形成是由于电子从导带 到量子阱态的跃迁造成的。 Kuhr 等 [12] 研究了高温退 火对 4H-SiC 晶体中堆垛层错的影响, 高温退火后 晶体中的堆垛层错密度大幅增加, 理论和实验结果 表明重掺杂氮会导致 4H-SiC 晶体中自发形成堆垛 层错。Kato 等 [13] 研究了在 4H-SiC 晶体生长过程中 重掺杂氮对堆垛层错的影响, 结果表明重掺杂氮的 生长区域会产生堆垛层错, 未掺杂氮的生长区域不 会产生堆垛层错。Kato 还发现堆垛层错产生于晶体 生长初期, 主要是由晶体生长初期速率较低, 氮掺 杂浓度相对较高导致的。Okojie 等 [14] 研究了 SiC 衬 底外延生长过程中堆垛层错的产生机理, 认为是衬 底与外延层间氮掺杂浓度差异引起的应力导致堆垛 层错的产生。道康宁(Dow Corning)公司研究发现当 碳化硅衬底中的氮浓度超过一定水平时, 衬底表面 的划痕处在高温退火时会形成堆垛层错 [15] [14,16] 。一般认为 SiC 晶体中的 图 1 平行和垂直于(1100)方向的晶体切片示意图 [13,18] 。 PVT 法 生长的 SiC 晶体存在一个生长小面, 由于生长机制 的不同 [19] , 晶体中小面区域氮浓度明显高于非小面 区域的氮浓度。不同于通常文献报道的氮浓度高容 易导致堆垛层错增多的规律 [13,18]…”