Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Núñez, Juan; Avedillo, M.J.; Quintana, J. M.

doi:10.1109/tvlsi.2013.2283306

Cited by 4 publications

(1 citation statement)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because the negative differential resistance (NDR) circuit has a special current-voltage (I-V) curve, it has been used in many digital and analog circuits after decades of development. In many NDR-based applications, its most special theoretical basis is a so-called monostable-bistable transmission logic element (MOBILE) [1]- [3]. The MOBILE is usually composed of two NDR circuits in series.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Full Adder Using Negative Differential Resistance Circuits Based on CMOS Process

Gan,

Zhang

2024

Preprint

View full text Add to dashboard Cite

We demonstrate a full adder design based on several MOS-NDR circuits connected in series and in parallel. A basic MOS-NDR circuit is made of thee standard Si-based metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. By adjusting the appropriate parameters of the gate width of the MOSFET, the Λ-type negative differential resistance (NDR) characteristic can be presented in its combined current-voltage (I-V) curve. The operating principle of this 1-bit full adder is based on the theory of monostable-bistable transmission logic gate (MOBILE). The bias voltage of this circuit is a clock signal, and its output voltage is a low or high logic level determined by the relative current peak conditions of the load and driver components of the MOBILE circuit. Most of the NDR-based applications designed in the general literature use resonant tunnel diode (RTD) devices as the main components. Compared with RTD device, our MOS-NDR circuit can be designed with standard CMOS process and simulated with HSPICE. We implement this full adder using 0.18 µm standard CMOS process.

show abstract

Section: Introductionmentioning

confidence: 99%