Experimental study on the 4H-SiC-based VDMOSFETs with lightly doped P-well field-limiting rings termination

He, Yunhua; Lv, Hong Liang; Tang, Xiao Yan; Qing, Song; Zhang, Yi Meng; Han, Chao; Zhang, Yu Ming

doi:10.1016/j.sse.2016.11.008

Cited by 5 publications

(1 citation statement)

References 13 publications

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“…A 50 nm thick gate oxide was fabricated by oxidation in dry O2 and anneal in NO ambient at 1250 °C, followed by Al deposition to form the gate electrode. [16] Fig. 1.…”

Section: Methodsmentioning

confidence: 99%

The Influence of Temperature Storage on Threshold Voltage Stability for SiC VDMOSFET

Bai

Tang

Han

et al. 2019

MSF

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Even with SiC power MOSFETs released into the commercial market, the threshold voltage instability caused by near interface states is still an attracting issue, which is a major obstacle to further improving the device performance. In this paper, the effects of temperature storage on the threshold voltage stability of n-channel 4H-SiC VDMOSFET are studied. It is found that the capture of hole traps is dominant during the long-term temperature storage at 425 K, causing a considerable negative shift of threshold voltage. In view of the influence of temperature storage, the positive and negative drift trends of threshold voltage slow down during the gate-bias stress measurement. And the ∆VTH, the difference between the threshold voltages recorded after positive and negative gate-bias stress in the same duration, also grows slowly with the increasing stress duration. Finally, some suggestions for improving the threshold reliability of n-channel SiC VDMOSFETs are presented.

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“…A 50 nm thick gate oxide was fabricated by oxidation in dry O2 and anneal in NO ambient at 1250 °C, followed by Al deposition to form the gate electrode. [16] Fig. 1.…”

Section: Methodsmentioning

confidence: 99%