Experimental study on carrier transport mechanism in ultrathin-body SOI MOSFETs

Uchida, Ken; Watanabe, Hiroshi; Koga, J.; Kinoshita, Atsuhiro; Takagi, Shinichi

doi:10.1109/sispad.2003.1233625

Cited by 35 publications

(39 citation statements)

References 9 publications

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“…The peak mobility in case of 5nm planar UTB SOI MOSFET (SiO 2 /Poly-Si gate stack reference) is μ peak = 408cm 2 /Vs and is very close to published data [21] [22]. For the NW MOSFETs (SiO 2 /Poly-Si reference) with a NW height of 6nm we observed a peak mobility of μ peak = 208cm 2 /Vs which is also similar to results published recently [23].…”

Section: Resultssupporting

confidence: 90%

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Schmidt

Gottlob

Bolten

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

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Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW-and UTB-nMOSFETs with conventional SiO 2 /Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data. IntroductionHigh-k dielectric gadolinium silicate (GdSiO) films with large band offsets to silicon, a dielectric constant of 16 provide an attractive scaling potential for future low power applications [1][2][3]. Thermal stability up to 1000°C -a key issue for gate first integration -has been demonstrated for uncapped films in combination with titanium nitride (TiN) electrodes [1][2][4].In addition to an excellent control of V th one dimensional nanostructures are potentially attractive increase of severely depressed SCE and higher I On /I Off ratios [5] [6].A major disadvantage of UTB SOI, FinFETs and NW MOSFETs however, is the concurrent increase of parasitic source to drain resistances, especially if silicon the thickness drops below 10 nm of the silicon film. This inherent feature may eventually be solved by selective epitaxy and/or silicided source drain leads [7][8]. One of the key features, the inversion channel mobility of MOSFETs, can not be extracted from standard split C/V measurements accurately if the high access resistance problem is not addressed appropriately [9].For UTB structures, a special mobility test structure has been proposed and applied to UTB SOI and sSOI devices [9]-[12]. This structure features contacts to the inversion channel to allow four-probe measurements where the series resistance effects can be eliminated. For NW-or FinFETs, however, this structure can not be employed as an inversion layer contact would disrupt the main transistor channel on the Fin/NW sidewall. Instead, we propose to use a different approach with several devices to extract the real series resistance and to correct the measured split C/V data. Experimental Device LayoutKey for the correct mobility (μ eff ) extraction by the split CV technique according to equation 1 is the exact knowledge of the voltage drop V DS inside the channel and the exact measurement of the inversion charge density Q inv . The other parameters in equ. 1 are the gate length L, the gate width W (extracted from TEM images) and the measured drain source current I DS .) (The proposed design for NW MOSFETs feature two "sense" contacts in addition to the conventional source and drain contacts (V L/R , Fig. 1). Furthermore, to address large gate areas and therefore to measure an adequate gate to channel capacitance, very long (L G =100μm) and multiple NWs in parallel are fabricated for split CV method. Fig. 1: Optical micrograph (top view) of a SOI NW nMOSFET with 400 NWs in parallel and additional contacts close to the channel (V L/R ). Q inv can be determined directly by integrating the gate channel capacitance C gc mea...

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Section: Resultssupporting

confidence: 90%

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Schmidt

Gottlob

Bolten

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

View full text Add to dashboard Cite

show abstract

“…At the transistor level, they translate into specifications for the OFF current, i.e., 599 must be 100 nA/µm in the case of HP devices and 100 pA/µm in the case of LP devices [40] [41]. [73] [74], holes in SOI [74], holes in germanium-on-insulator [75], graphene on SiO2 [76], graphene embedded in h-BN [61], InAs [77], WSe2 [78] [79], WS2 [81], black phosphorus [82] [83], MoS2 [84] [85], c) Experimental Rc of different 2D materials and thin body semiconductors compared with expectations of the ITRS. Data sources: ITRS [40], MoS2 [84], MoS2-2H/Au and MoS2-1T/Au [86], MoS2/Au [87] [88] and MoS2/Ni [87], Pd-Graphene [90], d) Scatter plot of delay time and power-delay product for High Performance Logic of different 2D Heterostructurebased FET and comparison with ITRS 2015 e) Scatter plot of delay time and power-delay product for Low Standby Power logic of different 2D Heterostructure-based FET and comparison with ITRS 2015.…”

Section: Figurementioning

confidence: 99%

Quantum engineering of transistors based on 2D materials heterostructures

et al. 2018

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Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

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“…It has been reported that surface roughness will induce an additional threshold energy in quantum well devices and this effect had been systematically measured in experiments, 9,32 i.e., enhanced threshold energy. Therefore, the observed threshold energy will be greater than that described by the more commonly understood body quantization effect according to ប 2 2 / ͑2m z T B 2 ͒.…”

Section: Effective Masses On Transmittivity and Threshold Energymentioning

confidence: 98%

Signatures of quantum transport through two-dimensional structures with correlated and anticorrelated interfaces

Low

Ansari

2008

Phys. Rev. B

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Electronic transport through a two-dimensional decananometer length channel with correlated and anticorrelated surfaces morphologies is studied using the Keldysh nonequilibrium Green's-function technique. Due to the pseudoperiodicity of these structures, the energy-resolved transmission possesses pseudoband and pseudogap. Channels with correlated surfaces are found to exhibit wider pseudobands than their anticorrelated counterparts. By surveying channels with various combinations of material parameters, we found that a smaller transport mass increases the channel transmittivity and energy bandwidth of the pseudobands. A larger quantization mass yields a larger transmittivity in channels with anticorrelated surfaces. For channels with correlated surfaces, the dependence of transmittivity on quantization mass is complicated by odd-to-even mode transitions. An enhanced threshold energy in the energy-resolved transmission can also be observed in the presence of surface roughness. The computed enhanced threshold energy was able to achieve agreement with the experimental data for Si͗110͘ and Si͗100͘ devices.

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Experimental study on carrier transport mechanism in ultrathin-body SOI MOSFETs

Cited by 35 publications

References 9 publications

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Quantum engineering of transistors based on 2D materials heterostructures

Signatures of quantum transport through two-dimensional structures with correlated and anticorrelated interfaces

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