Experimental research on performance degradation of TSV microstructure under thermal cycling, vibration and electrical stress

Fan, Zhengwei; Chen, Xun; Wang, Yashun; Jiang, Yu; Zhang, Shufeng

doi:10.1016/j.microrel.2022.114643

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…The Bosch process is characterized by alternating the etching and passivating steps during the multiple-cycle structure fabrication, which naturally leaves a periodic scallop on the sidewall of a hole. The scallops may cause stress concentration, which results in the cracking of the dielectric and barrier layers deposited on the sidewall [ 8 ]. The stress may be enhanced in a subsequent thermal process, especially when the edges of the scallop are sharp.…”

Section: Introductionmentioning

confidence: 99%

Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application

Feng

Zeng

et al. 2022

Micromachines

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In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-μm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10−10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10−9 A after a DC voltage was kept at 100 V for 200 s.

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Section: Introductionmentioning

confidence: 99%