Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

Adhikari, Prottay M.; Hooshyar, Hossein; Vanfretti, Luigi

doi:10.1109/access.2019.2911916

Cited by 6 publications

(3 citation statements)

References 23 publications

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“…. It is to be noted that the NI reference PMU utilizes a certified synchrophasor estimation algorithm based on a generic recursive DFT algorithm as is discussed in [50]. The PMU reference is also equipped with a module NI 9227 for measuring current synchrophasors but this paper is only focused on the voltage synchrophasor.…”

Section: System Descriptionmentioning

confidence: 99%

A Low-Cost Test Platform for Performance Analysis of Phasor Measurement Units

Kunac,

Petrović,

Despalatović

et al. 2024

Electronics

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In this paper, a customizable low-cost voltage waveform generator based on a real-time desktop PC and embedded data acquisition card synchronized with Coordinated Universal Time (UTC) is presented. A software approach to phase-locked loop synchronization with an external Global Positioning System (GPS) pulse signal is utilized to achieve a time uncertainty of ±1μs. This avoids expensive hardware modules for synchronization and timing purposes, which are commonly presented in literature. Besides the application for controlling the test platform, our own phasor data concentrator (PDC) application is running concurrently on the host PC. The latter is used for collecting and comparing the syncrophasor data from the test platform against the syncrophasor data measured by phasor measurement units (PMUs) under the test. The paper describes all procedures for generating reference test signals. Numerous case studies were performed, and experimental results for steady-state compliance as well as frequency ramp and phase modulation tests for dynamic compliance are presented in detail. All tests confirm that customizable test platform meets the requirements of IEEE/IEC standards. Compared to other calibrators, the cost as well as the specifications and point-by-point concept of data processing makes the described test platform suitable for performance analysis of PMU algorithms implemented on various development boards.

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Section: System Descriptionmentioning

confidence: 99%

A Low-Cost Test Platform for Performance Analysis of Phasor Measurement Units

Kunac,

Petrović,

Despalatović

et al. 2024

Electronics

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“…The aforementioned external PMUs (the hardware used is that reported in [42] and extended in [43]) were connected to the low-voltage analog outputs of the real-time simu-lator. It is crucial to note that these PMU designs feature both current and voltage inputs to function as PMUs whereas Typhoon HIL 604 hardware only provides analog voltage outputs.…”

Section: Hardware Integrationmentioning

confidence: 99%

Real-Time Control of a Battery Energy Storage System Using a Reconfigurable Synchrophasor-Based Control System

Adhikari,

Vanfretti,

Chang

et al. 2023

Energies

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Synchrophasor-driven smart grid applications aiming to orchestrate a diverse set of Distributed Energy Resources (DERs) require extensive infrastructure including substantial instrumentation hardware, communication network extensions and controller installations for coordinated operation. This can make the overall installation expensive. Additionally, due to the computational complexity and data-intensive nature of the PDC functionality, most of the existing PDC implementations are on a purely software level, making them unsuitable for the real-time applications. To address this, the current paper proposes an alternate architecture for the real-time synchrophasor-based control of DER applications (e.g., microgrids) incorporating a centralized synchronization hardware designed to replace aggregation Phasor Data Concentrators (PDCs) and supplementary control algorithms into a singular reconfigurable hardware. This particular hardware is termed a Synchrophasor Synchronization Gateway and Controller (SSGC). The robustness of the proposed architecture is tested by using real-time (RT) Controller Hardware-In-the-Loop (CHIL) simulation-based experiments by manipulating the communication network that connects the SSGC with multiple Phasor Measurement Unit (PMU) streams broadcasting data through the IEEE C37.118.2 protocol in real time. These PMU streams were generated by using a real-time microgrid model running on a Typhoon HIL 604 simulator. To manipulate the communication interface between the proposed SSGC hardware and the PMU streams, a configurable Wide Area Network (WAN) emulator and communication network impairment appliance deployed in the Candela Technologies CT910 external hardware was utilized. The real-time control system was expanded by incorporating a low-pass filter to eliminate the potential overswitching of a Battery Energy Storage System (BESS). The proposed architecture demonstrated a reliable performance under ideal to moderately tampered communication networks. However, under a significantly corrupted network, the performance of this architecture is acutely affected.

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“…The second technique uses an interpolated DFT (IpDFT), where interpolation between frequency components adjacent to the mains frequency are used to obtain a better accuracy of the magnitude and phase of the mains voltage or current. AdhiKari [17] used the national instruments (NI) RIObased platform and its PMU implementation to investigate different FPGA realizations of PMUs. The algorithm included in the NI advanced PMU development system, uses an iterative interpolated DFT described by Paolone [18].…”

Section: Related Workmentioning

confidence: 99%

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

Kikkert

2019

Electronics

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Phasor measurement units (PMU) are increasingly used in electrical power transmission networks, to maintain stability and protect the network. PMUs accurately measure voltage, phase, frequency, and rate of change of frequency (ROCOF). For reliability, it is desirable to implement a PMU using an FPGA. This paper describes a novel algorithm, suited to implementation in an FPGA and based on a simple PMU block diagram. A description of its realization using low hardware complexity infinite impulse response (IIR) filters is given. The IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems, describes "reference" Finite Impulse Response (FIR) filters for implementing PMU hardware. At the 10 kHz sampling frequency used for our implementation, each "reference" FIR filter requires 100 multipliers, while an 8th order IIR filter only requires 12 multipliers. This paper compares the performance of different order IIR filter-based PMUs with the performance of the same PMU algorithm using the IEC/IEEE FIR reference filter. The IIR-based PMU easily satisfies all the requirements of IEC/IEEE standard and has a much better out of band signal rejection performance than a FIR-based PMU. Steady state errors for a rated voltage ± 10% and a rated frequency ± 5 Hz are < 0.000001% for total vector error (TVE) and < 1 µHz for frequency, with a latency of two mains cycles.

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Experimental Quantification of Hardware Requirements for FPGA-Based Reconfigurable PMUs

Cited by 6 publications

References 23 publications

A Low-Cost Test Platform for Performance Analysis of Phasor Measurement Units

A Low-Cost Test Platform for Performance Analysis of Phasor Measurement Units

Real-Time Control of a Battery Energy Storage System Using a Reconfigurable Synchrophasor-Based Control System

A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

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