2010 Silicon Nanoelectronics Workshop 2010
DOI: 10.1109/snw.2010.5562573
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Experimental progress of and prospects for nanomagnet logic (NML)

Abstract: We present the current state-of-the-art of nanomagnetic logic (NML), which is one of the beyond-Moore device technologies being pursued within the SRC-NRI (Nanoelectronics Research Initiative). Advantages of NML include low power and non-volatility. We show that all key ingredients for NML architectures have been demonstratedincluding logic, fan-out, and on-chip clock structures. Input and output can be accomplished in a fashion similar to MRAM technology. As such, NML is CMOS compatible.

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Cited by 4 publications
(5 citation statements)
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“…For example, [60] predicts that a NAND FO1 in 15 nm CMOS will have a footprint of ∼70 000 nm 2 . From [61] a majority logic gate constructed from magnets with 60 × 90 nm 2 footprints will itself have a net footprint of ∼68 000 nm 2 . Moreover, not only can a majority gate be programmed to perform a NAND function, it is inherently a more computationally powerful gate.…”
Section: Scalabilitymentioning
confidence: 99%
“…For example, [60] predicts that a NAND FO1 in 15 nm CMOS will have a footprint of ∼70 000 nm 2 . From [61] a majority logic gate constructed from magnets with 60 × 90 nm 2 footprints will itself have a net footprint of ∼68 000 nm 2 . Moreover, not only can a majority gate be programmed to perform a NAND function, it is inherently a more computationally powerful gate.…”
Section: Scalabilitymentioning
confidence: 99%
“…The QCA, SET, and NML technologies can be considered as cascade-friendly, with supporting evidence provided by the designs of a QCA 32-bit adder [13] , a SET 16-bit adder [22] , and an NML 32-bit adder [23] . In CMOS-free MTJ designs and newly developed DNA nanotechnology, however, we have not encountered any cascading of M gates that is longer than two.…”
Section: Cascadingmentioning
confidence: 92%
“…However, the highest fan-out degree in the work just cited is 3. The highest encountered fan-out of 3 also applied to NML [23] . It appears that higher fan-out should be achievable via increasing the required energy for the clocking field [23] .…”
Section: Fan-outmentioning
confidence: 99%
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“…The ability to create SiDBs at atomically precise locations and the exhibited tendency for charge configurations to settle to the ground state constrained by screened Coulombic repulsion [1][2][3] lends this technology well for field-coupled nanocomputing (FCN), a class of devices that employ electric 8,9 or magnetic field effects 10,11 for operation. SiDB logic components demonstrated experimentally by Huff et al 1 provide an example of this by taking advantage of the charge sharing behavior between closely-situated SiDBs to represent binary logic states, wherein the position of a charge in pairs of SiDBs can be used to encode bit information.…”
Section: Introductionmentioning
confidence: 99%