Experimental Platform for Accelerate the Training of ANNs with Genetic Algorithm and Embedded System on FPGA

Fe, Jorge; Aliaga, Ramón J.; Gadea, R.

doi:10.1007/978-3-642-38622-0_43

Cited by 1 publication

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Phase 3: Optimization of the topology of neural networks by means of heterogeneous evolutionary computation [15]. With this method, it is very important to be able to secure, and evaluate, the capacity for generalization of the optimal neural network obtained.…”

Section: Evolutionary Optimization Methodsmentioning

confidence: 99%

“…2 and 3, and it can be seen that different technologies are suited to training different sizes of neural networks: -For 2 15 training samples (shown in Fig. 2a), our training run with an FPGA Cyclone IV (100 MHz coprocessor clock) was faster than a Tesla C1060 GPU (602 MHz core clock ) when the number of neurons in the hidden layer was less than 20 (topology of the ANN: 6-20-20-1).…”

Section: Training Of Neural Networkmentioning

confidence: 99%

See 1 more Smart Citation

Evolutionary optimization of neural networks with heterogeneous computation: study and implementation

Aliaga

Gironés

2015

J Supercomput

View full text Add to dashboard Cite

In the optimization of Artificial Neural Networks (ANNs) via Evolutionary Algorithms (EAs) and the implementation of the necessary training for the objective function, there is often a trade-off between efficiency and flexibility. Pure software solutions on general-purpose processors tend to be slow because they do not take advantage of the inherent parallelism, whereas hardware realizations usually rely on optimizations that reduce the range of applicable network topologies, or they attempt to increase processing efficiency by means of low-precision data representation. This paper presents, first of all, a study that shows the need of heterogeneous platform (CPU-GPU-FPGA) to accelerate the optimization of ANNs using genetic algorithms and, secondly, an implementation of a platform based on embedded systems with hardware accelerators implemented in FPGA (Field Pro-grammable Gate Array). The implementation of the individuals on a remote low-cost Altera FPGA allowed us to obtain a 3x-4x acceleration compared with a 2.83 GHz Intel Xeon Quad-Core and 6x-7x compared with a 2.2GHz AMD Opteron Quad-Core 2354.

show abstract

Section: Evolutionary Optimization Methodsmentioning

confidence: 99%

Section: Training Of Neural Networkmentioning

confidence: 99%