Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

Grossi, Alessandro; Vianello, E.; Zambelli, Cristian; Royer, Pablo; Noël, Jean-Philippe; Giraud, B.; Perniola, L.; Olivo, P.; Nowak, E.

doi:10.1109/tvlsi.2018.2805470

Cited by 61 publications

(37 citation statements)

References 30 publications

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“…Figure 1 presents the switching operations of a bipolar OxRAM. The electroforming step (in green) required by some RRAM technologies [24] [6] in order to create a first oxygen vacancies-based conductive filament is not considered here and assumed to be already performed. Then, the OxRAM can be switched from Low Resistance State (LRS) to High Resistance State (HRS) by reset operation (in red) or from HRS to LRS by a set operation (in blue).…”

Section: A Bipolar Resistive Switching Memoriesmentioning

confidence: 99%

“…Compensating the VT loss by increasing the gate polarity (gate overdrive) leads to increased complexity, reliability issues and more complex voltage management. In [6] [7] [8] [9], the reset gate voltage is raised between 2.4 up to 6V in order to perform a fast reset. The high voltages considered will cause stress in (i) the selected bitcell transistor, (ii) the neighbors bitcells selectors sharing the same BL and WL and in (iii) the near memory array periphery.…”

Section: Polarity Gate (Pg)mentioning

confidence: 99%

“…And that for a standard 6 nanowire PCT [15], current from few micro-amperes up to 100µA can be achieved without gate overdrive. Regarding the literature, we considered a 60µA programming current which is usually considered as a reliable programming current [6] [36] [34]. Finally, Figure 8 presents a full set-reset programming cycle in 1PCT1R configuration showing a short 100ns set operation and a 22µs reset operation.…”

Section: A Pct-based Oxram Operationmentioning

confidence: 99%

“…As expected, the 1T1R bitcell requires a huge gate overdrive to perform sub-100µsec reset time. As a reference, 1T1R bitcells demonstrated in the literature require more from 3 to 5V to enable sub-100ns reset operations [6] [7] [8]. Figure 15 presents the evolution of the programming time of the previously mentioned bitcells.…”

Section: Figure 14: Set Time Versus Bl-sl Voltage Difference For Minimentioning

confidence: 99%

“…When used with bipolar RRAM technologies, unipolar MOS selectors cannot perform equally in each polarity and lead to strongly unbalanced programming operations [5] and strongly overdriven selector during reset operation [6] [7] [8] [9], (leading to faster aging of the selector). To overcome this issue, we propose the use of Polarity Controllable Transistors (PCT) such as the multiple independent all-around gate transistors [10] which are opening a new era in microelectronic circuit design.…”

Section: Introductionmentioning

confidence: 99%

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Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

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Section: A Bipolar Resistive Switching Memoriesmentioning

confidence: 99%

Section: Polarity Gate (Pg)mentioning

confidence: 99%

Section: A Pct-based Oxram Operationmentioning

confidence: 99%

Section: Figure 14: Set Time Versus Bl-sl Voltage Difference For Minimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

Self Cite

View full text Add to dashboard Cite

show abstract

Differentiable Content Addressable Memory with Memristors

Pedretti

Graves

Vaerenbergh

et al. 2022

Adv Elect Materials

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Memristors, Flash, and related nonvolatile analog device technologies offer in‐memory computing structures operating in the analog domain, such as accelerating linear matrix operations in array structures. These take advantage of analog tunability and large dynamic range. At the other side, content addressable memories (CAM) are fast digital lookup tables which effectively perform nonlinear Boolean logic and return a digital match/mismatch value. Recently, nonvolatile analog CAMs have been presented merging analog storage and analog search operations with digital match/mismatch output. However, CAM blocks cannot easily be inserted within a larger adaptive system due to the challenges of training and learning with binary outputs. Here, a missing link between analog crossbar arrays and CAMs, namely a differentiable content addressable memory (dCAM), is presented. Utilizing nonvolatile memories that act as a “soft” memory with analog outputs, dCAM enables learning and fine‐tuning of the memory operation and performance. Four applications are quantitatively evaluated to highlight the capabilities: improved data pattern storage, improved robustness to noise and variability, reduced energy and latency performance, and an application to solving Boolean satisfiability optimization problems. The use of dCAM is envisioned as a core building block of fully differentiable computing systems employing multiple types of analog compute operations and memories.

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Recent Progress in Real‐Time Adaptable Digital Neuromorphic Hardware

Kornijcuk

Jeong

2019

Advanced Intelligent Systems

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It has been three decades since neuromorphic engineering was first brought to public attention, which aimed to reverse‐engineer the brain using analog, very large‐scale, integrated circuits. Vigorous research in the past three decades has enriched neuromorphic systems for realizing this ambitious goal. Reverse engineering the brain essentially implies the inference and learning capabilities of a standalone neuromorphic system—particularly, the latter is referred to as embedded learning. The reconfigurability of a neuromorphic system is also pursued to make the system field‐programmable. Bearing these desired attributes in mind, recent progress in digital neuromorphic hardware is overviewed, with an emphasis on real‐time inference and adaptation. Real‐time adaptation, that is, learning in realtime, highlights the feat of spiking neural networks with inherent rich dynamics, which allows the networks to learn from environments embodying an enormous amount of data. The realization of real‐time adaptation imposes severe constraints on digital neuromorphic hardware design. Herein, the constraints and recent attempts to cope with the challenges arising from the constraints are addressed.

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Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

Cited by 61 publications

References 30 publications

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Differentiable Content Addressable Memory with Memristors

Recent Progress in Real‐Time Adaptable Digital Neuromorphic Hardware

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