Experimental Extraction of the Charge Centroid and of the Charge Type in the P/E Operation of Sonos Memory Cells

Abstract

In this work, we report experiments on SONOS memory cells aimed to investigate the vertical position and the nature of the charge trapped in the gate stack during Program/Erase (P/E) cycling. To this purpose a new experimental setup has been developed to accurately detect the amount of injected charge and the consequent threshold voltage shift. The results, confirmed by different measurement techniques, show that the position of the charge centroid during program and erase operation is quite insensitive to the injection conditions. Moreover, we investigate by means of carrier separation experiments the role of the different type of carriers during program and erase operation of SONOS cells.

Impact of the charge transport in the conduction band on the retention of Si-nitride based memories

“…9, which is due to the complex balance of drift, diffusion, PF emission and capture fluxes. In these thick oxides the spatial profiles of the trapped charge are still consistent with the measurements in [14] but different from those assumed in [7], consequently m * N and ν T values are also different. Fig.…”

Reliability of 3D NAND Flash Memories

“…Moreover, electrons and holes going through blocking layer and tunnel layer from the storage layer contribute in a marginal, but not negligible, way to oxide degradation. During erasing (right), the hot hole injection from the substrate generates interface traps at the oxide/nitride interface, causing several damages to both storage and tunnel layers, as well as electrons transfer through the tunnel layer [11]. The generation of such interface traps between oxide and nitride interface is the main cause of endurance degradation: in programmed cells, electrons sitting in shallow traps can easily escape via oxide damages induced by cycling, resulting in a charge reduction that may cause read errors.…”

“…2.8), while drain and source are left floating. Erase operation occurs either through electron detrapping from the storage layer or hole injection from the substrate into the storage layer; at the same time, such operation causes an electron injection from the control gate to the storage layer through FN tunneling, and this is the reason for the well-known "erase saturation" problem [11]. The results of charge separation experiments [12] demonstrate that both electron detrapping and holes injection mechanisms contribute to the erase of a previously programmed CT device: electron detrapping dominates the first part of the transient, whereas hole injection prevails after the removal of the trapped electron charge due to electron emission.…”

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

“…We assume that the active traps are uniformly distributed in the nitride layer (according to experimental analyses on nitride charge centroid previously reported in the literature [16]), with distributed energies following a Gaussian law (σ=0.2eV, ΔET=1.8eV [17]). …”