International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
DOI: 10.1109/iedm.2001.979588
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Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs

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Cited by 61 publications
(51 citation statements)
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“…Likewise, a reduction in the DOS, in this case to 0.7× its original value (for both N C and N V ), gives an additional offset as expected based on (5). In fact, the ratio of the DOS and mobility in the reference device and the thin device [hence, the prefactor in (5)] can be found by extrapolating ln(η rat ) to 1000/T → 0, i.e., when the last term in (6) reduces to zero. Indeed, the additional increase in the offset of ln(η rat ) is in agreement with the expected value of ln(1/0.7).…”
Section: Separation Of δμ and δDosmentioning
confidence: 99%
See 1 more Smart Citation
“…Likewise, a reduction in the DOS, in this case to 0.7× its original value (for both N C and N V ), gives an additional offset as expected based on (5). In fact, the ratio of the DOS and mobility in the reference device and the thin device [hence, the prefactor in (5)] can be found by extrapolating ln(η rat ) to 1000/T → 0, i.e., when the last term in (6) reduces to zero. Indeed, the additional increase in the offset of ln(η rat ) is in agreement with the expected value of ln(1/0.7).…”
Section: Separation Of δμ and δDosmentioning
confidence: 99%
“…The effect of quantum confinement on the electrical UTB device characteristics is generally quantified using the shift in threshold voltage V TH as metric [6], [9]- [12]. Hence, changes in the band alignment are expected to contribute to a shift in V TH since, in case of band gap widening, a higher gate bias is required to obtain the same inversion charge density.…”
Section: Introductionmentioning
confidence: 99%
“…Further lateral scaling is going to require scaling of the channel thickness (t ch ) as well. However, as t ch scales down, carrier transport in the channel deteriorates, mainly as a consequence of the increased carrier scattering mechanisms [14], [15]. In this paper, we have explored a solution to this problem through the introduction of a pure thin layer of InAs in the channel [16], [17].…”
mentioning
confidence: 99%
“…In SOTB technology, scalability can be pursued by reducing the SOI and BOX thicknesses. The minimum SOI thickness is considered to be 6 nm, after which the influence of the quantum effect or mobility degradation appears (Uchida et al, 2001). Given this value and considering the thickness variation, the minimum gate length of the SOTB CMOSFET is expected to be about 20 nm while maintaining a small V th variation (Sugii et al, 2009).…”
Section: Resultsmentioning
confidence: 99%