2012 Proceedings of the ESSCIRC (ESSCIRC) 2012
DOI: 10.1109/esscirc.2012.6341361
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Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS

Abstract: We present a silicon characterization vehicle implementing six different constructions of intrinsic Physically Unclonable Functions (PUFs). The design contains four different memory-based PUFs, one of which is a novel buskeeper PUF, and two different delay-based PUFs. Test chips are fabricated in 65 nm Low Power (LP) technology, using a standard cell ASIC design flow for the memory-based PUFs and a full custom flow for the delay-based ones. This test vehicle enables a comprehensive experimental evaluation of i… Show more

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Cited by 102 publications
(43 citation statements)
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References 5 publications
(4 reference statements)
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“…In CMOS technologies, the widely discussed SRAM PUF reads out the power-up patterns, which are ideally random and unique for different cells and dies [4], [7]. The entropy source of the SRAM PUF is process variations in a pair of matched invertors, resulting in the different pull-up and pull-down strengths.…”
Section: A Bit Instability In Pufsmentioning
confidence: 99%
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“…In CMOS technologies, the widely discussed SRAM PUF reads out the power-up patterns, which are ideally random and unique for different cells and dies [4], [7]. The entropy source of the SRAM PUF is process variations in a pair of matched invertors, resulting in the different pull-up and pull-down strengths.…”
Section: A Bit Instability In Pufsmentioning
confidence: 99%
“…A PUF implemented in commercial silicon technology enables chip level cryptographic functions such as secret key generation, entity authentication and IP protection [1]- [4]. Ideally, a silicon PUF utilizes intrinsic sources of variation on devices or interconnections, to extract a unique data pattern which is unpredictable and reproducible in various noisy environments.…”
Section: Introductionmentioning
confidence: 99%
“…This is no surprise, since SRAM PUFs were found to be the most reliable and unique PUFs in [9,13]. Furthermore, the number of PUF cells per mm 2 is also highest for the SRAM PUF.…”
Section: Mutual Informationmentioning
confidence: 76%
“…Unfortunately two Latch PUFs per ASIC are unusable due to faults in the addressing logic. Furthermore, during preliminary testing, one DFF instance was found to be very unreliable when compared to the other instances (also noted in [9,13]). This instance we also excluded from the test data.…”
Section: Data Setmentioning
confidence: 99%
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