Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases

Abstract

We have implemented three concurrent fault simulation algorithms and applied them to several circuit families. The algorithms we've implemented are concurrent fault simulation (CFS), hierarchical concurrent fault simulation (HCFS), and a modification to HCFS called bundled hierarchical fault simulation (BHCFS). In BHCFS, a structure is imposed upon the simulation error lists which can cause significant reduction in simulation run time. A prototype of each algorithm has been applied to circuit families of varying size to generate actual run time data. The circuits are scaleable (to some granularity) in gate COWL This property allows the simulator run time data to be presented as a function of circuit size without the effects of varying circuit topology. In this report, we present the description and run time data for several such circuits.