Image placement (IP) and overlay error specifications are serious concerns for lithography at each successive technology node. Some of the primary contributors to image placement error (IPE) in EUV lithography are reticle and chuck surface non-flatness and chucking flatness non-uniformity. Flatness compensation has been proposed as a method to relax flatness specification for EUV substrates. However, in order for flatness compensation to work effectively, the various components of IPE i.e., reticle flattening and as-chucked z-height variation needs to be estimated accurately. Flatness compensation models assume a completely flat, rigid chuck and conformal clamping of the reticle backside. In this paper we will describe experiments designed to verify the different assumptions that the flatness compensation models are based on. The experiments involve printing wafers using a set of reticles of different flatness specifications on the ASML EUV Alpha Demo Tool (ADT) in Albany, NY. We will discuss results from these experiments and use Finite Element Modeling to simulate reticle chucking to correlate these results to physical properties electrostatic chuck on the ADT.
INTRODUCTIONReticle Non-flatness in EUV Lithography results in Image Placement Error. The specifications for IPE get tighter with each successive technology node. In order to achieve the wafer IPE from reticle non-flatness, the P-V as-chucked reticle non-flatness should be 30nm or better as recommended by the ITRS for 2014 production. Current state of the art EUV substrate flatness is ~90nm P-V [3] for each reticle surface. In order to improve substrate flatness, EUV substrate vendors employ aggressive polishing techniques. These polishing techniques generate substrate defects, which typically require additional cleaning steps during substrate manufacture to remove them. Substrate defects can severely affect device performance. As a result, flatter substrates are more expensive and require more time to fabricate. In order to relax substrate flatness specifications, researchers have proposed the use of flatness compensation schemes. Flatness compensation [4] is a method of applying appropriate pattern offsets during E-beam writing to correct for placement errors due to mask non-flatness. With a viable flatness compensation scheme, the reticle flatness specifications can be greatly relaxed.