Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions

Lv, Yang; Bloom, Robert P.; Wang, Jian Ping

doi:10.1109/lmag.2019.2957258

Cited by 30 publications

(17 citation statements)

References 19 publications

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“…The fact that the circuit can learn around variations can be useful not just for classical machine learning tasks like classification or unsupervised learning but also for tasks that have been demonstrated on probabilistic computers like optimization 2,40 , inference 41,42 or invertible logic 24,29 .…”

Section: Variation-tolerant Learning Of a Full-addermentioning

confidence: 99%

“…This poses an obstacle to deploy these systems for real-world application on a large scale while preserving high reliability. Several approaches have been proposed to overcome these challenges on a device level for example by applying external magnetic fields 24 , performing a calibration phase 2 or by post-processing 25 . Another interesting approach to counter the effect of variability and realize high-performance in neuromorphic systems is to perform training and inference on the same hardware system 26,27 .…”

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confidence: 99%

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Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

et al. 2022

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One of the big challenges of current electronics is the design and implementation of hardware neural networks that perform fast and energy-efficient machine learning. Spintronics is a promising catalyst for this field with the capabilities of nanosecond operation and compatibility with existing microelectronics. Considering large-scale, viable neuromorphic systems however, variability of device properties is a serious concern. In this paper, we show an autonomously operating circuit that performs hardware-aware machine learning utilizing probabilistic neurons built with stochastic magnetic tunnel junctions. We show that in-situ learning of weights and biases in a Boltzmann machine can counter device-to-device variations and learn the probability distribution of meaningful operations such as a full adder. This scalable autonomously operating learning circuit using spintronics-based neurons could be especially of interest for standalone artificial-intelligence devices capable of

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Section: Variation-tolerant Learning Of a Full-addermentioning

confidence: 99%

mentioning

confidence: 99%

Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

et al. 2022

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“…This has been demonstrated experimentally in ref. 48,49 where a stable MTJ was used as a bipolar resistor whose distribution was tuned by an external field. Fig.…”

Section: B Performing the Bsn Functionmentioning

confidence: 99%

Quantitative Evaluation of Hardware Binary Stochastic Neurons

Hassan

Datta

2021

Phys. Rev. Applied

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Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by leveraging the existing Magnetic RAM (MRAM) technology that has integrated 1T-1MTJ cells in ∼ Gbit densities. The 3T-1SR design however can be realized using different materials or devices that provide naturally fluctuating resistances. Extending previous work, we evaluate hardware BSNs from this general perspective by classifying necessary and sufficient conditions to design a fast and energy-efficient BSN that can be used in scaled Ising Machine implementations. We connect our device analysis to systems-level metrics by emphasizing hardware-independent figures-of-merit such as flips per second and dissipated energy per random bit that can be used to classify any Ising Machine.

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“…Another example is the implementation of logic gates by defining E to be zero for all {s} that belong to the truth table, and have some positive value for those that do not 23 . Unlike standard digital logic, such a BM-based implementation would provide invertible logic that not only provides the output for a given input, but also generates all possible inputs corresponding to a specified output 23,45 .…”

Section: Ising Modelmentioning

confidence: 99%

Probabilistic computing with p-bits

Kaiser,

Datta

2021

Preprint

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Digital computers store information in the form of bits that can take on one of two values 0 and 1, while quantum computers are based on qubits that are described by a complex wavefunction whose squared magnitude gives the probability of measuring either a 0 or a 1. Here we make the case for a probabilistic computer based on p-bits which take on values 0 and 1 with controlled probabilities and can be implemented with specialized compact energy-efficient hardware. We propose a generic architecture for such p-computers and show that they can significantly accelerate randomized algorithms used in a wide variety of applications including but not limited to Bayesian networks, optimization, Ising models and quantum Monte Carlo.

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Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions

Cited by 30 publications

References 19 publications

Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions

Quantitative Evaluation of Hardware Binary Stochastic Neurons

Probabilistic computing with p-bits

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