Experimental Demonstration of Holey Silicon-Based Thermoelectric Cooling

Ren, Zongqing; Cao, Jiahui; Lim, Jungyun; Yu, Ziqi; Kim, Jae Choon; Lee, Jaeho

doi:10.1109/ted.2022.3166867

IEEE Trans. Electron Devices

2022

DOI: 10.1109/ted.2022.3166867

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Experimental Demonstration of Holey Silicon-Based Thermoelectric Cooling

Zongqing Ren

Jiahui Cao

Jungyun Lim

et al.

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Cited by 4 publications

(1 citation statement)

References 39 publications

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“…This transistor-scale TEC is directly integrated on the side of an SOI transistor, enabling effective lateral heat redistribution for local hotspots. Such a lateral TEC design offers a unique cooling method specifically for SOI technology, taking advantage of the sustained temperature gradient in the device layer and overcoming the limitation of poor vertical heat dissipation due to the BOX layer [28], [29]. We first demonstrate the TEC design for cooling a single transistor then extend our work to a TEC array design with multiple individual coolers that can provide spatial temperature control.…”

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confidence: 93%

Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling

Luo,

Lim,

Chen

et al. 2024

IEEE Trans. Electron Devices

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Silicon-on-insulator (SOI) technology offers many advantages for transistors while also presenting significant challenges in thermal management. The buried oxide (BOX) layer impedes vertical heat dissipation, rendering conventional cooling solutions based on air and liquid coolers inefficient. In this study, we propose a novel theoretical design of a holey silicon-based lateral thermoelectric cooler (TEC) that provides a unique cooling solution for SOI transistors. By redistributing heat laterally, this TEC overcomes the limitation of poor vertical heat dissipation caused by the BOX layer, meanwhile taking advantage of the sustained temperature gradient in the device layer. In addition, we present a novel precooling strategy which utilizes a long-time, optimal-voltage TEC cooling pulse to cool down a short-time, high-power-density heating pulse. We evaluate the cooling performance through simulation of two devices: an SOI transistor-TEC device and a 5 × 5 SOI transistor-TEC array device. Under a 10 µs transient heat pulse with high-power density of 11 000 W/cm 2 (1.6 W), the SOI transistor-TEC device with a 10 µm thick BOX layer can be cooled from 465.7 • C down to 407.4 • C ( T = 58.3 • C) in peak hotspot temperature when precooled with a 1000 µs TEC pulse, consuming 0.20 W of TEC power. Furthermore, the SOI transistor-TEC array device provides spatial temperature control by incorporating multiple coolers which enable selective cooling for individual transistor units without significant loss of cooling performance. In summary, our TEC design exhibits great potential in offering dynamic thermal management for a wide range of advanced SOI devices.

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confidence: 93%

Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling

Luo,

Lim,

Chen

et al. 2024

IEEE Trans. Electron Devices

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A novel cascaded thin-film thermoelectric cooler for on-chip hotspot cooling

Gong

Shi

et al. 2023

Applied Thermal Engineering

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Machine learning-assisted thermoelectric cooling for on-demand multi-hotspot thermal management

Luo,

Lee

2024

Journal of Applied Physics

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Thermoelectric coolers (TECs) offer a promising solution for direct cooling of local hotspots and active thermal management in advanced electronic systems. However, TECs present significant trade-offs among spatial cooling, heating, and power consumption. The optimization of TECs requires extensive simulations, which are impractical for managing actual systems with multiple hotspots under spatial and temporal variations. In this study, we present a novel machine learning-assisted optimization algorithm for thermoelectric coolers that can achieve global optimal temperature by individually controlling TEC units based on real-time multi-hotspot conditions across the entire domain. We train a convolutional neural network with a combination of the inception module and multi-task learning approach to comprehend the coupled thermal-electrical physics underlying the system and attain accurate predictions for both temperature and power consumption with and without TECs. Due to the intricate interaction among passive thermal gradient, Peltier effect and Joule effect, a local optimal TEC control experiences spatial temperature trade-off which may not lead to a global optimal solution. To address this issue, we develop a backtracking-based optimization algorithm using the machine learning model to iterate all possible TEC assignments for attaining global optimal solutions. For any m × n matrix with NHS hotspots (n, m ≤ 10, 1 ≤ NHS ≤ 20), our algorithm is capable of providing 52.4% peak temperature reduction and its corresponding TEC array control within an average of 1.64 s while iterating through tens of temperature predictions behind-the-scenes. This represents a speed increase of over three orders of magnitude compared to traditional finite element method strategies which take approximately 27 min.

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Experimental Demonstration of Holey Silicon-Based Thermoelectric Cooling

Cited by 4 publications

References 39 publications

Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling

Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling

A novel cascaded thin-film thermoelectric cooler for on-chip hotspot cooling

Machine learning-assisted thermoelectric cooling for on-demand multi-hotspot thermal management

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