Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits

Abstract

This paper performs an experimental comparative study between t h e W a v e l a y o u t s t y l e ( " S " s h a p e g a t e g e o m e t r y ) a n d t h e Conventional (rectangular gate geometry) counterpart in order to verify and quantify the benefits that Wave structure can bring to improve the performance of devices in analog circuit, specially in trasconductance the ratio of transconductance between drain current as a function of the ratio of the drain current normalized by the geometric factor and frequency response (voltage gain and unit voltage gain frequency). By working with Wave structure instead of conventional counterpart, it can improve the device performance in terms of drain current in the triode and saturation regions, consequently better results in the transconductance and unit voltage gain frequency gains.

Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment

“…The higher LEF in the drain region of the superior semicircle is responsible for generating a higher IDS than the one found in the inferior semicircle. In addition to that, it was demonstrated that the WnM IDS is higher than the one found in the standard layout (CnM), considering the same gate area (AG) and bias conditions (6)(7)(8).…”

“…Even though, the MOSFET implemented with Wave layout style, as observed in Figure 1, operates at the same time as the superior semicircle in the IDBC and the inferior semicircle in the EDBC (6). Note that the Longitudinal Electrical Field (LEF) varies in the channel length (L) (6)(7)(8) and it is higher in the drain region of the superior semicircle, because the drain region area of the superior semicircle (AD_IDBC) is smaller than the inferior semicircle area (AD_EDBC) (6-8). The higher LEF in the drain region of the superior semicircle is responsible for generating a higher IDS than the one found in the inferior semicircle.…”

Total ionizing dose radiation effects between the Wave layout style and its conventional counterpart focusing on the digital IC applications

“…The higher ε // ur u in the drain region of the superior semicircle is responsible for creating a higher average drift velocity of the mobile carriers in the channel ( υ // u r u ) in the superior semicircle than the one observed in the inferior semicircle and consequently I DS in the superior semicircle is higher than the one found in the inferior semicircle, but the resultant of the WnM is higher than the CnM [3,10,11]. Furthermore, the superior and inferior WnM semicircles present different drain/source series resistances due to the different drain/source regions areas [3,10,11]. Observing Figure 2, it can be verified that the superior semicircle (IDBC), the source series resistance (R S ) is smaller than the one observed in the inferior semicircle (EDBC), due to the drain region area of the superior semicircle (A D_IDBC ) is smaller than the one found in the drain region area of the inferior semicircle (A D_EDBC ) [12].…”

“…Observing Figure 1, it can be found that each semicircle of the WnM is biased in two different modes. The superior semicircle is biased in IDBC, while the inferior semicircle is biased in external drain bias configuration (EDBC) [3,10,11]. Besides that, ε // ur u varies along of its channel length (L) [3,10,11] and it is higher in the drain region of the superior semicircle than the one found in the drain region of the inferior semicircle, due to the drain region area of the superior semicircle (A D_IDBC ) is smaller than the one observed in the inferior semicircle (A D_EDBC ) [3,10,11].…”

“…Besides that, ε // ur u varies along of its channel length (L) [3,10,11] and it is higher in the drain region of the superior semicircle than the one found in the drain region of the inferior semicircle, due to the drain region area of the superior semicircle (A D_IDBC ) is smaller than the one observed in the inferior semicircle (A D_EDBC ) [3,10,11]. The higher ε // ur u in the drain region of the superior semicircle is responsible for creating a higher average drift velocity of the mobile carriers in the channel ( υ // u r u ) in the superior semicircle than the one observed in the inferior semicircle and consequently I DS in the superior semicircle is higher than the one found in the inferior semicircle, but the resultant of the WnM is higher than the CnM [3,10,11]. Furthermore, the superior and inferior WnM semicircles present different drain/source series resistances due to the different drain/source regions areas [3,10,11].…”