Experimental Characterization and Application of Circuit Architecture Level Single Event Transient Mitigation

Mohr, K.C.; Clark, Lawrence T.

doi:10.1109/relphy.2007.369909

Cited by 7 publications

(1 citation statement)

References 17 publications

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“…Other SET induced errors can include writes to multiple cells or writes from read out cells to others, in the case where a WL glitches on after the bit lines (BLs) are fully driven but before BL precharging occurs. Experimental measurements have shown that simply increasing the array size so as to have large SET immune drivers is largely impractical [39].…”

Section: Memory Circuit Peripheral Errorsmentioning

confidence: 99%

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Clark

Patterson

Ramamurthy

et al. 2016

IEEE Trans. Comput.

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A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart-only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm 2 /mg LET EFF . We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.Index Terms-Radiation hardening by design (RHBD); microprocessor; cache memory; total ionizing dose; single event transients, soft error mitigation, single-event effects.

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Section: Memory Circuit Peripheral Errorsmentioning

confidence: 99%