Experiences with UPC on TILE-64 processor

Serres, Olivier; Anbar, Ahmad; Merchant, Saumil G.; El‐Ghazawi, Tarek

doi:10.1109/aero.2011.5747452

Cited by 9 publications

(8 citation statements)

References 7 publications

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“…Chapman et al [7] implemented the X10 programming language on the Intel SCC (using RCCE library) and performed a comparative study versus MPI using different benchmark applications. Serres et al [37] ported Berkeley UPC to Tilera's many-core Tile64.…”

Section: Pgas Researchmentioning

confidence: 99%

See 1 more Smart Citation

Exploring cross-layer power management for PGAS applications on the SCC platform

Gamell

Rodero

Parashar

et al. 2012

Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing

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Section: Pgas Researchmentioning

confidence: 99%

“…For example, existing PGAS research includes improvement of UPC collective operations [36], hybrid models to improve performance limitations [11] and the implementation of X10 for the Intel SCC [7] and UPC for Tilera's many core [37].…”

Section: Motivationmentioning

confidence: 99%

Exploring cross-layer power management for PGAS applications on the SCC platform

Gamell

Rodero

Parashar

et al. 2012

Proceedings of the 21st International Symposium on High-Performance Parallel and Distributed Computing

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“…Singh et al [2011] and Suh et al [2012] report the performance of FFTW and FFT/CRBlaster, respectively, on the Tilera Maestro platform. Serres et al [2011] report on the performance of UPC implemented over GasNet plus Pthreads/OperaMPI on a TilePro 64. UPC versions of NPB 2.2 under class A show better performance for Pthreads than MPI for benchmarks with significant communication components under strong scaling experiments (input class A).…”

Section: Fpu Resultsmentioning

confidence: 99%

NoCMsg

Zimmer

Mueller

2015

ACM Trans. Archit. Code Optim.

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The number of cores of contemporary processors is constantly increasing and thus continues to deliver ever higher peak performance (following Moore's transistor law). Yet high core counts present a challenge to hardware and software alike. Following this trend, the network-on-chip (NoC) topology has changed from buses over rings and fully connected meshes to 2D meshes.This work contributes NoCMsg, a low-level message-passing abstraction over NoCs, which is specifically designed for large core counts in 2D meshes. NoCMsg ensures deadlock-free messaging for wormhole Manhattan-path routing over the NoC via a polling-based message abstraction and non-flow-controlled communication for selective communication patterns. Experimental results on the TilePro hardware platform show that NoCMsg can significantly reduce communication times by up to 86% for single packet messages and up to 40% for larger messages compared to other NoC-based message approaches. On the TilePro platform, NoCMsg outperforms shared memory abstractions by up to 93% as core counts and interprocess communication increase. Results for fully pipelined double-precision numerical codes show speedups of up to 64% for message passing over shared memory at 32 cores. Overall, we observe that shared memory scales up to about 16 cores on this platform, whereas message passing performs well beyond that threshold. These results generalize to similar NoC-based platforms. ACM Reference Format:Christopher Zimmer and Frank Mueller. 2015. NoCMsg: A scalable message-passing abstraction for networkon-chips. ACM Trans.

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“…Similar many-core coprocessor systems include the Intel 80-core Terascale coprocessor (Mattson et al, 2008), the 48-core single-chip cloud computer (SCC) (Mattson et al, 2010; Vangal et al, 2008), the 64-core Tilera Tile64 SoC (Bell et al, 2008; Serres et al, 2011) and the recent Intel Xeon Phi accelerator (Heinecke et al, 2013). Use of low power ARM based SoC processors (Mitra et al, 2013) and many-core accelerators such as the TI C66X DSP (Igual et al, 2012; Stotzer et al, 2013) for high-performance computing are also of increasing interest.…”

Section: Related Work and Comparison With Other Systemsmentioning

confidence: 99%

Programming the Adapteva Epiphany 64-core network-on-chip coprocessor

Varghese

Edwards

Mitra

et al. 2015

The International Journal of High Performance Computing Applica

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In the construction of exascale computing systems energy efficiency and power consumption are two of the major challenges. Low-power high performance embedded systems are of increasing interest as building blocks for large scale highperformance systems. However, extracting maximum performance out of such systems presents many challenges. Various aspects from the hardware architecture to the programming models used need to be explored. The Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore strategies for implementing scientific applications on memory constrained low-powered devices such as the Epiphany. With future systems expected to house thousands of cores in a single chip, the merits of such architectures as a path to exascale is compared to other competing systems.

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Experiences with UPC on TILE-64 processor

Cited by 9 publications

References 7 publications

Exploring cross-layer power management for PGAS applications on the SCC platform

Exploring cross-layer power management for PGAS applications on the SCC platform

NoCMsg

Programming the Adapteva Epiphany 64-core network-on-chip coprocessor

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