Experiences with concurrent fault simulation of diagnostic programs

Demba, S.; Ulrich, Ernst G.; Lentz, K.P.; Giramma, D.

doi:10.1109/43.55192

Cited by 10 publications

(2 citation statements)

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“…These subtests can be graded by manual analysis. For proper evaluation, most subtests should be simulated or manually analyzed in the order of program execution [4]. With careful selection, some subtests could be graded in parallel for cycle time reduction.…”

Section: Paper 43 95mentioning

confidence: 99%

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CAE functionality for verification of diagnostic programs

Pyron

Sallade

Proceedings. 'Meeting the Tests of Time'., International Test Conference

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6500 Chase Oaks Blvd., Piano, TX 75023 (214) 575-2590 STRACTVerification of embedded built-in t e s t (BIT) diagnostic programs is typically accomplished by manual analysis and fault insertion techniques. Digital fault simulation offers the opportunity to automate the verification of BIT. Frequently, fault simulators do not support the capacity to completely simulate and fault grade a BIT. A feasibility study conducted by Texas Instruments has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT verification through fault simulation. With a n example, this paper illustrates the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. Introduct ionEmbedded digital diagnostic programs are a form of built-in test (BIT). For the purpose of this paper, diagnostic program refers to the BIT software or firmware used to functionally test the digital portion of a system. BIT provides an automated test capability for detection and isolation of system failures. The BIT uses the resident processors to control and execute a stored program to test the system functionally.Diagnostic programs usually a r e structured hierarchically into subtests targeted to the various functional blocks of the system architecture [ll. A common technique for structuring the diagnostic test is to have each subtest determine the correct functionality of a portion of the circuit. This technique is frequently referred to as the "startsmall" or "kernel" approach [2]. Subtests that execute later in the testing sequence may assume that the previously verified circuitry is fault-free.A processor-based diagnostic test program may be centralized or distributed yet still be hierarchical in nature [21. After the execution of the test for a module, the diagnostic program typically would continue execution of additional tests for other functions and modules of the system. Each functional p a r t of t h e module is t e s t e d i n sequence. Ideally, the diagnostic program is structured so that each test or functional group of tests is a separate, complete software program routine. To verify the functionality and fault coverage of the BIT program, test engineers frequently use manual analysis techniques along with fault insertion [3]. Manual analysis provides a measure of the ability of the diagnostic test to meet r e q u i r e m e n t s . Since m a n u a l a n a l y s i s is subjective, r e s u l t s will vary based on t h e engineer's experience, judgment, and objectivity. Thorough manual analysis requires a great deal of time and detailed knowledge of both the hardware and diagnostic program design.Physical fault insertion provides a statistical validation of the manual analysis results. To achieve a high confidence level in the estimated coverage, however, engineering support personnel must insert many faults. This process is timeconsuming and inefficient.While manual analysis and fault insertion techniques have verified diagnostic programs, the traditiona...

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Section: Paper 43 95mentioning

confidence: 99%

“…The identification and removal of hyperactive faulty machines [4] frees t h e simulator resources to process the remaining faulty machines. The hyperactive faulty machines can be processed e i t h e r i n a s e p a r a t e simulation (later), or they can be evaluated by m a n u a l e n g i n e e r i n g a n a l y s i s .…”

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confidence: 99%