Materials integration can advance the performance of III-V semiconductor devices through the incorporation of wafer bonded template substrates. The objective of this study was to develop III-V based wafer bonded templates for subsequent epitaxial growth of device structures using noncompliant layers. In this study, III-V layers are transferred to other III-V substrates using hydrogen ion exfoliation and wafer bonding. The incorporation of high resolution x-ray scattering techniques has proven to be particularly helpful for the development of this materials system. For example, studies of the blistering and exfoliation of different III-V materials was aided by the use of high resolution diffraction scans and atomic force microscopy. The kinetics of exfoliation for many different III-V materials (including GaAs, InP, InAs, and GaSb) showed similar dependence on the processing temperature relative to the material melting temperature (and other materials parameters). In all of these cases, a multiple annealing sequence was shown to produce the most efficient exfoliation.
IntroductionNew developments with III-V materials may be based on device structures that are not currently accessible because of the lack of a suitable substrate. Materials integration through wafer bonding represents a viable approach to address this issue and the technique is well known for certain types of semiconductor applications. This technique is most widely employed for silicon-on-insulator (SOI) structures [1, 2], but also for post-epitaxy device processing of III-V structures. [3][4][5][6][7][8][9][10][11] SOI is also used for subsequent epitaxial deposition. [12] In addition, for both III-V and silicon-based systems, compliant substrate technologies have been investigated as a means to accommodate lattice mismatch between a layer and a substrate. [13][14][15][16][17] However, rigid composite III-V substrates, with a high resistivity bulk component and a large lattice parameter template layer for subsequent epitaxial deposition have not been extensively developed and the strain state for many III-V composite structures has not been reported or understood in terms of the wafer bonding or subsequent processing conditions.The fabrication of III-V composite wafer bonding has the ultimate goal of producing virtual substrates for advanced III-V devices. [A virtual substrate is one that does not necessarily possess the lattice parameter of binary compounds.] An example of a simple composite wafer is shown in Figure 1. The main processing steps to produce this structure follow: In this particular example, a dielectric such as silicon nitride is ECS Transactions, 2 (5) 3-13 (2006) 10.1149/1.2204874, copyright The Electrochemical Society 3 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 128.171.57.189 Downloaded on 2015-06-13 to IP 4deposited on both GaAs (handle) and InP (template) substrates [the bonding subsequently occurs at the dielectric / dielectric interface]. Th...