Execution Model of Three Parallel Languages: OpenMP, UPC and CAF

Marowka, Ami

doi:10.1155/2005/914081

Cited by 6 publications

(6 citation statements)

References 13 publications

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“…The naive UPC implementation in Section 3.2 shows the easy programmability of UPC that is fully comparable with OpenMP, as discussed in e.g. [20]. The first code transformation, in form of explicit thread privatization shown in Section 4.1, may be done by automated code translation.…”

Section: Resultsmentioning

confidence: 99%

“…This can be precisely calculated when the values of m and n, as well as the thread grid layout, are known. Formula(20) is essentially the same as (13) from Section 5.2.5. It is commented that S local thread in(20) denotes the total volume of all local messages (in both horizontal and vertical directions) per thread, likewise denotes S remote thread the total volume of all remote messages, with C remote thread denoting the number of remote messages per thread.…”

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confidence: 99%

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Performance Optimization and Modeling of Fine-Grained Irregular Communication in UPC

Lagravière

Langguth

Prugger

et al. 2019

Scientific Programming

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The UPC programming language offers parallelism via logically partitioned shared memory, which typically spans physically disjoint memory sub-systems. One convenient feature of UPC is its ability to automatically execute between-thread data movement, such that the entire content of a shared data array appears to be freely accessible by all the threads. The programmer friendliness, however, can come at the cost of substantial performance penalties. This is especially true when indirectly indexing the elements of a shared array, for which the induced between-thread data communication can be irregular and have a fine-grained pattern. In this paper we study performance enhancement strategies specifically targeting such fine-grained irregular communication in UPC. Starting from explicit thread privatization, continuing with block-wise communication, and arriving at message condensing and consolidation, we obtained considerable performance improvement of UPC programs that originally require fine-grained irregular communication. Besides the performance enhancement strategies, the main contribution of the present paper is to propose performance models for the different scenarios, in form of quantifiable formulas that hinge on the actual volumes of various data movements plus a small number of easily obtainable hardware characteristic parameters. These performance models help to verify the enhancements obtained, while also providing insightful predictions of similar parallel implementations, not limited to UPC, that also involve between-thread or between-process irregular communication. As a further validation, we also apply our performance modeling methodology and hardware characteristic parameters to an existing UPC code for solving a 2D heat equation on a uniform mesh. MotivationGood programmer productivity and high computational performance are usually two conflicting goals in the context of developing parallel code for scientific computations. Partitioned global address space (PGAS) [10,2,11,22], however, is a parallel programming model that aims to achieve both goals at the same time. The fundamental mechanism of PGAS is a global address space that is conceptually shared among concurrent processes that jointly execute a parallel program. Data exchange between the processes is carried out by a low-level network layer "under the hood" without explicit involvement from the programmer, thus providing good productivity. The shared global address space is logically partitioned such that each partition has affinity to a designated owner process. This awareness of data locality is essential for achieving good performance of parallel programs written in the PGAS model, because the globally shared address space may actually encompass many physically distributed memory sub-systems.Unified Parallel C (UPC) [13,28] is an extension of the C language and provides the PGAS parallel programming model. The concurrent execution processes of UPC are termed as threads, which execute a UPC program in the style of single-program-multiple-...

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

Performance Optimization and Modeling of Fine-Grained Irregular Communication in UPC

Lagravière

Langguth

Prugger

et al. 2019

Scientific Programming

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“…The design of a parallel programming model that meets all of these expectations is still out of reach [2, 10-12, 21, 22, 24, 28]. Still, despite the many obstacles, there has been some progress in parallel programming that brings us closer to the desired parallel programming model [12].…”

Section: Introductionmentioning

confidence: 99%

TBBench: A Micro-Benchmark Suite for Intel Threading Building Blocks

Marowka¹

2012

Journal of Information Processing Systems

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Abstract-Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.

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“…However, despite the many obstacles, there has been enough progress in parallel programming to bring us closer to the desired parallel language [23]. Two main parallel programming paradigms are widely used for developing scientific and engineering applications: shared-memory (SM) and distributed-shared-memory (DSM) parallel programming models.…”

Section: Introductionmentioning

confidence: 99%

Bsp2omp: A Compiler For Translating Bsp Programs To Openmp

Marowka

2009

International Journal of Parallel, Emergent and Distributed Sys

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The convergence of the two widely used parallel programming paradigms, sharedmemory and distributed-shared-memory parallel programming models, into a unified parallel programming model is crucial for parallel computing to become the next mainstream programming paradigm. We study the design differences and the performance issues of two parallel programming models: a shared-memory programming model (OpenMP) and a distributed-shared programming model (BSP).The study was carried out by designing a compiler for translating BSP parallel programs to an OpenMP programming model called BSP2OMP. Analysis of the compiler outcome, and of the performance of the compiled programs, show that the two models are based on very similar underlying principles and mechanisms.

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Execution Model of Three Parallel Languages: OpenMP, UPC and CAF

Cited by 6 publications

References 13 publications

Performance Optimization and Modeling of Fine-Grained Irregular Communication in UPC

Performance Optimization and Modeling of Fine-Grained Irregular Communication in UPC

TBBench: A Micro-Benchmark Suite for Intel Threading Building Blocks

Bsp2omp: A Compiler For Translating Bsp Programs To Openmp

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