Excess loop delay in continuous-time delta-sigma modulators

Cherry, James A.; Snelgrove, W.M.

doi:10.1109/82.755409

Cited by 265 publications

(138 citation statements)

References 28 publications

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“…However, this noise floor is about 10 dB higher. This degradation is likely to be due to the excess loop delay and clock jitter [19,21]. Measured voltage waveforms on the detection electrodes are shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…There is no require- ment for a phase compensator as it would be in a low-pass sigma-delta modulator. To derive a CT M from its equivalent discrete-time (DT) architecture, a multi-feedback topology should be adopted [19]. There are two different digital to analogue converters (DAC) required in the local feedback paths to each electronic resonator; a half-return-zero (HRZ) DAC and a return-zero (RZ) DAC.…”

Section: System Level Simulationmentioning

confidence: 99%

See 1 more Smart Citation

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

Dong

Kraft

Hedenstierna

et al. 2008

Sensors and Actuators A: Physical

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Section: Resultsmentioning

confidence: 99%

Section: System Level Simulationmentioning

confidence: 99%

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

Dong

Kraft

Hedenstierna

et al. 2008

Sensors and Actuators A: Physical

View full text Add to dashboard Cite

“…In (3), the reference value CCF t for calculating CC i , is a cross-correlation result of the first set sample with the test pattern. It is a constant denominator D in (7). Therefore, division is only calculated once per frame of data.…”

Section: Methodsmentioning

confidence: 99%

“…ELD degrades the performance of the modulator and can even lead to an unstable modulator [7]. Therefore, in this design, a fixed half clock cycle delay between the quantizer and the feedback DACs is allocated.…”

Section: Excess Loop Delaymentioning

confidence: 99%

A continuous-time delta-sigma ADC with integrated digital background calibration

Tan

Miao

Palm

et al. 2016

Analog Integr Circ Sig Process

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This work presents a digital calibration technique in continuous-time (CT) delta-sigma (DR) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT DR converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

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“…ELD is normally caused by the nonzero switching time of the transistors in the quantizer and the DAC [2,3]. Due to ELD, when Non-Return-to-Zero (NRZ) feedback is used, a part of the feedback pulse will be shifted into the next clock cycle which may lead to system instability [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

Cai

Yang

Sin

et al. 2013

Analog Integr Circ Sig Process

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The design and optimization methodology for CT RD modulators with hybrid Active-Passive (AP) loopfilters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the hybrid AP loop filtering can achieve an approximated noise-shaping function as a fully active DR modulator with the same order. The ELD effect in the hybrid AP CT DR modulator which influences the poles and zeros locations of the Noise Transfer Function (NTF) in the modulator is depicted. This paper also investigates the feasibility of applying the ELD compensation techniques that were used to be implemented in the active integrator's case to the hybrid AP CT DR modulator; however, some of them cannot be practically applied since the passive loop-filter cannot perform proportional feedback signal summation. After the discussion and analysis, the technique similar to Vadipour et al. (In: Symposium on VLSI circuits digest of technical papers, 2008) can be easily implemented at circuit-level and after applying it, there is one additional zero to compensate the peak in the NTF. With the help of this technique, the maximum quantizer delay tolerance can be a full clock period. The mentioned ELD compensation technique was applied in a 2nd order CT DR modulator with an active-RC integrator as the 1st stage and a passive RC filter as the 2nd stage, which was verified by transistor-level simulations in 65 nm CMOS. The circuit exhibits either 67.3 dB or 65.3 of SNDR, under the effect of half clock period or one clock period ELD, respectively; by contrast, without compensation, the system is unstable with both half or one clock period ELD effect. The designed hybrid CT DR modulator achieves 2 MHz signal bandwidth and consumes 2.54 mW of power.

show abstract

Excess loop delay in continuous-time delta-sigma modulators

Cited by 265 publications

References 28 publications

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

A continuous-time delta-sigma ADC with integrated digital background calibration

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

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