Exceptional thermal strain reduction by a tilting pillar architecture: Suspended Ge layers on Si (001)

Abstract

In this paper we present the exceptional thermal strain release provided by micrometric Si pillar arrays to Ge epitaxial patches suspended on them, for different pillar aspect ratios and patch sizes. By combining 3D and 2D Finite Element Method simulations, low-energy plasma-enhanced chemical vapor deposition on patterned Si substrates, μ-Raman, μ-photoluminescence and XRD measurements, we provide a quantitative and consistent picture of this effect with the patch sizes. Strain relaxation up to 85% of the value for the corresponding planar films can be obtained for a squared patch 100 μm in size. Finally, the enhanced thermal strain relaxation is analytically explained in terms of the Si pillar lateral tilting, critically dependent on the pillar aspect ratio, very similarly to the well-known case of a deflected beam. Our results are transferable to any material deposited, or wafer bonded at high temperature, on any patterned substrate: wafer bowing can be controlled by micrometric patterned features well within the present capabilities of deep reactive ion etching

Dislocation-Free SiGe/Si Heterostructures

“…It has been further demonstrated that merging can also be obtained directly during growth (by raising the growth temperature) [21,31]. The suspended film is found [18] to still profit of the ability of the underlying pillars to release thermal strain by tilting. Despite displaying a good crystal quality, suspended films do display some defects, likely to be created during actual merging [21].…”

“…The vertical morphology offers two key advantages with respect to common 2D layers. On one hand, the free surface surrounding the crystals allows for very efficient relaxation of the thermal-stress field [15][16][17][18], therefore avoiding cracking. On the other hand, 60 • dislocations forming at the Ge/Si interface and laying on (111) planes, are confined to the bottom of the crystal only (no 60 • defect can reach the region located at a height h >1.4 b, where b is the Si pillar base width).…”

GaAs epilayers grown on patterned (001) silicon substrates via suspended Ge layers

“…The GaAs structure grown on the Ge suspended layer is a solid, uniform and continuum layer without voids or holes. The SEM measurements also show the absence of cracks in the Ge and GaAs layer, confirming that the thermal stress induced by the annealing and GaAs growth on the structure is released through the deformation of the Si pillars 31 .

Figure 3Cross-section SEM image of the whole structure of Sample A. It is possible to distinguish the separated Si pillars at the bottom, the merged Ge layer and the GaAs layer on the top.

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“…This Ge layer is free from TD and lattice matched with the GaAs. It can efficiently relax the thermal strain which can arise between the epilayer and Si substrate as a consequence of the growth procedure, thus avoiding the formation of cracks 31 . In addition, the three-dimensional modulated (hilly) surface of the suspended layer, owing to its intrinsic curvature, permits the formation, via annealing induced step bunching, of double-height steps on the Ge surface.…”

Growth and Coalescence of 3C-SiC on Si(111) Micro-Pillars by a Phase-Field Approach

“…Among them, a promising approach consists of growing the SiC film suspended on top of micrometer sized Si pillars, deeply etched into the substrate. It has been shown, indeed, that such an architecture is very effective in relieving strain by exploiting the additional degree of freedom of pillar tilting and rotation [7], allowing for a significant reduction of wafer bowing even with several μm thick SiC layers [8].…”