Excellent Reliability of Xtacking™ Bonding Interface

Ouyang, Yu; Yang, Sen; Yin, Dandan; Huang, Xiang; Wang, Zhiqiang; Yang, Shengwei; Han, Kun; Xia, Zhongyi

doi:10.1109/irps46558.2021.9405115

Cited by 13 publications

(11 citation statements)

References 16 publications

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“…Present work was focused on memory cell arry. The selecting MOSFETs could be formed on the top of the flash devices or with Xtacking TM technique, which the memory cells and peripheral circuits are fabricated on two different wafers and then bonded together [17].…”

Section: Architecture and Process Methodsmentioning

confidence: 99%

A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture

Huang

Zhu

et al. 2022

IEEE Electron Device Lett.

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A novel 3D NOR memory array with singlecrystal silicon channel, high-density and fast-read was proposed and fabricated. The proposed 3D NOR memory is investigated in terms of device structure, integration scheme, and circuit architecture. To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices, and 3) unlike 3D NAND, bit-line planes, source-line planes and vertical word-lines were utilized. Due to the use of single-crystal silicon channels, our memory devices have large read currents of 110 µA/µm. Through programming/erasing tests, the programming speed of 10 µs and erasing speed of 100 ms were obtained, which are comparable to that of the 2D NOR Flash with single-crystal silicon channels.

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Section: Architecture and Process Methodsmentioning

confidence: 99%

A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture

Huang

Zhu

et al. 2022

IEEE Electron Device Lett.

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“…Under the premise of not improving the process to ensure storage reliability, the use of 3D stacking technology to further increase the storage capacity per unit physical area has become a new trend [5]. Currently, the mainstream 3D stacking technologies include BiCS [6], P-BiCS [7], VNAND [8], TCAT [9], and Xtacking from YMTC [10], among others. The flash memory units in 3D flash blocks are stacked in a three-dimensional manner, and the flash memory units on the same level form a "layer" structure [2].…”

Section: D Stackingmentioning

confidence: 99%

Flash storage technology status and development research

2023

J. Phys.: Conf. Ser.

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Data storage devices are an important component of computer systems. Solid-state Drives, which use NAND Flash technology, are widely used in various fields due to their unique advantages such as high read-write speed, low power consumption, shock resistance, and small size compared to traditional mechanical hard drives. This paper first discusses the basic structure and principles of Flash memory, including floating gate transistors for storing and reading charges. Based on the current state of NAND Flash-based solid-state hard drives, this paper discusses key technologies and characteristics such as flash memory types, wear leveling, garbage collection, etc. It explores their features, advantages and limitations, and finally reasonably deduces the future development trend of Flash devices.

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“…A simplified cross-sectional view of a 3D NAND Flash test chip is shown in Figure 1. Two stacking wafers are connected together by millions of bonding interface vias (BIVs) [17,18]. As shown in the figure, the ESD pad on the backside of the upper wafer is connected to the ESD clamp circuit on the lower wafer through BIVs in between the two wafers [21][22][23][24].…”

Section: Esd Clamp Device Structurementioning

confidence: 99%

“…As shown in Figure 9, the FIB result exhibits cross-wafer and cross-layer burn-out, in which the upper and lower substrates are not shown. From the figure, it can be seen that the melted region involves both the upper wafer and the lower wafer [17], and device damage spreads across all metal layers and vias. Therefore, , this HBM failure not only causes large area burn-out of the pad in the horizontal direction but also induces damage from the pad down to the ESD clamp in the vertical direction.…”

Section: Analysis Of Substrate Resistancementioning

confidence: 99%

“…Nowadays, NAND Flash memory is widely used in mass storage applications. Threedimensional NAND Flash memory with 3D stacked IC (SIC) [17,18] is the most viable solution for high-capacity storage and low-bit-cost non-volatile memory [19,20]. During the contact-type usage, the pins of packaged die may be exposed to ESD sources such as human fingers; hence, ESD immunity is required for NAND Flash memory.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

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Excellent Reliability of Xtacking™ Bonding Interface

Cited by 13 publications

References 16 publications

A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture

A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture

Flash storage technology status and development research

Analysis of HBM Failure in 3D NAND Flash Memory

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