Exact Computing Multiplier Design using 5-to-3 Counters for Image Processing
Perumal B,
Balamanikandan A,
Jayakumar S
et al.
Abstract:This work presents a novel approach to improve the area and energy efficiency of 5:3 counter, a key element used in digital arithmetic. To provide an effective substitute for addition operations, mostly in the partial product reduction stage of larger multipliers, this study suggests a new 5:3 counter. The Input Shuffling Unit (ISU) is employed within the proposed 5:3 counter to minimize gate-level implementation and path delay during partial product reduction in 16-bit and larger multipliers, thereby enhancin… Show more
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