Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

Lau, John H.

doi:10.1109/isapm.2011.6105753

Cited by 150 publications

(46 citation statements)

References 170 publications

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“…In Heterogeneous 3D integration has also been widely explored to overcome bandwidth and energy challenges for LSI chips. Details on some of the recent progress in 3D integration can be found in [5,17,18]. Stacking of LSI chips reduces the footprint and decreases the interconnect length allowing high bandwidth density interconnects between chips.…”

Section: Emerging Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-tochip communication.

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Section: Emerging Methodologiesmentioning

confidence: 99%

Chip-to-chip interconnect integration technologies

Zia

Zhang

Yang

et al. 2016

IEICE Electron. Express

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“…The 3DIC packaging technologies exploit a z-axis dimension to provide a volumetric packaging solution for higher integration and performance, as well as to save space by stacking either separate chips or separate packages in a single package [11]. The two types of 3DIC packaging technologies are coined as "die stacking" or "package stacking" technologies [12]. Die stacking is the process of mounting multiple chips on top of each other vertically within a single package.…”

Section: Dic Packagingmentioning

confidence: 99%

“…They are vertically bonded together in either the wafer-to-wafer (W2W) or die-to-wafer form, using metalized pillars as the interconnection matter [12]. The TSV formation process can be divided simply into the following four steps: (1) drilling holes on a silicon wafer through etching or laser techniques; (2) filling these holes with conductive materials; (3) thinning the chips; and (4) bonding the stacked chips.…”

Section: Dic Tsvmentioning

confidence: 99%

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Technology Evaluation and Selection of 3DIC Integration Using a Three-Stage Fuzzy MCDM

Lee

Chou

2016

Sustainability

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Abstract:For the purpose of the sustainable development in the global semiconductor industry, emerging three-dimensional integrated circuit (3DIC) integration technologies have demonstrated their importance as potential candidates for extending the lifespan of Moore's Law. This study aimed to explore a technology selection process involving a three-stage fuzzy multicriteria decision-making (MCDM) approach to facilitate the effective assessment of emerging 3DIC integration technologies. The fuzzy Delphi method was first used to determine the important criteria. The fuzzy analytic hierarchy process (fuzzy AHP) was then adopted to derive the weights of the criteria. The fuzzy technique for order of preference by similarity to ideal solution (fuzzy TOPSIS) was finally deployed to rate the alternatives. Empirical results indicate that market potential, time-to-market, and heterogeneous integration are the top three decision criteria for the selection of 3DIC integration technologies. Furthermore, 2.5D through-silicon interposer (TSI) is of primary interest to the Taiwanese semiconductor industry, followed by 3DIC through-silicon via (TSV), 3D packaging, and 3D silicon TSV (Si TSV). The proposed three-stage fuzzy decision model may potentially assist industry practitioners and government policy-makers in directing research and development investments and allocating resources more strategically.

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“…Lau J.H. [10][11][12] presented an origin of 3D integration, discussed the evolution, challenges, and outlook of 3D IC/Si integrations, and proposed a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages with various passive TSV interposes. Yen Y.G [13] elaborated the effect of TSV parameters on the thermal equivalent conductivity of TSV interposer , and studied the effect of TSV interposer on thermal performance of the package based on the objective of compact modeling.…”

Section: Introductionmentioning

confidence: 99%

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

Li¹,

Zou²,

Shang³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The transmission performance of TSV considering the effect of electronic-thermal coupling is an new challenge in three dimension integrated circuit. This paper presents the thermal equivalent circuit (TEC) model of the TSV, and discussed the thermal equivalent parameters for TSV. Si layer is equivalent to transmission line according to its thermal characteristic. Thermal transient response (TTR) of TSV considering electronic-thermal coupling effects are proposed, iteration flow electronic-thermal coupling for TSV is analyzed. Furthermore, the influences of TTR are investigated with the noncoupling and considering coupling for TSV. Finally, the relationship among temperature, thickness of SiO 2 , radius of via and frequency of excitation source are addressed, which are verified by the simulation.

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Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

Cited by 150 publications

References 170 publications

Chip-to-chip interconnect integration technologies

Chip-to-chip interconnect integration technologies

Technology Evaluation and Selection of 3DIC Integration Using a Three-Stage Fuzzy MCDM

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

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