Events and constraints: a graphical editor for capturing logic requirements of programs

Smith, Margaret; Holzmann, Gerard J.; Etessami, Kousha

doi:10.1109/isre.2001.948539

Cited by 39 publications

(43 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Subtle errors in logic expressions may also be hard to identify and may lead to false positives and false negatives during verification and testing. This observation lead (prior to RCAT) to the design of the Timeedit tool [14], shown in Figure 1, where the fundamental concept is that of a time line upon which events are laid out. A timeline is a graphical depiction of a progression in time, stating behavior requirements that can be used to create formal properties for the SPIN model checker.…”

Section: Notation Design Principlesmentioning

confidence: 99%

See 1 more Smart Citation

Requirements Capture with RCAT

Smith

Havelund

2008

2008 16th IEEE International Requirements Engineering Conference

View full text Add to dashboard Cite

show abstract

Section: Notation Design Principlesmentioning

confidence: 99%

“…Note, however, that state machines here are used for expressing requirements and not designs. As will be outlined, the design of RCAT is responsive to experiences with and reflections on building or applying other requirements capture notations at JPL, such as the timeline editor [14], and the already mentioned LTL, and Büchi automata.…”

Section: Introductionmentioning

confidence: 99%

Requirements Capture with RCAT

Smith

Havelund

2008

2008 16th IEEE International Requirements Engineering Conference

View full text Add to dashboard Cite

show abstract

“…MTD's have several advantages over other graphical notations such as Live Sequence Charts (LSC's) [DH01] and Timeline [SHE01], in terms of expressiveness and efficient formal analysis. Live Sequence Charts (LSC's) are a modification of MSC's that allow specification of universal properties.…”

Section: Related Workmentioning

confidence: 99%

“…The Timeline notation [SHE01] has also been used to specify universal properties of asynchronous systems. It is limited, however, to describing a single totally ordered sequence of events.…”

Section: Related Workmentioning

confidence: 99%

“…First, the model is highly asynchronous and nondeterministic in nature. Second, there is significant prior work in model checking such systems (e.g., [SHE01,PR99]), which gave us a reasonable way to gauge the utility of MTD's. Finally, the inherent modularity in these systems made the application of compositional reasoning an attractive option.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Visual Specifications for Modular Reasoning about Asynchronous Systems

Amla

Namjoshi

Trefler

2002

Formal Techniques for Networked and Distributed Sytems — FORTE 2002

View full text Add to dashboard Cite

Abstract. We propose a framework that closely ties together visual specification and modular reasoning of asynchronous systems. The basis of the framework is a new notation, called Modular Timing Diagrams (MTD's), for specifying the universal properties about causality and timing of events in an asynchronous system. MTD's are complementary in nature to Message Sequence Charts, that are typically used to specify existential properties. Our framework includes two algorithms for formal reasoning with MTD's. The first is an efficient polynomial-time model checking algorithm. The second is an algorithm for automatically generating an assume-guarantee partitioning of an MTD, that exploits its inherent decompositional structure. We show how to use this decomposition for modular reasoning with MTD properties in conjunction with an asynchronous compositional reasoning rule. To illustrate the notation and our method, we describe a case study where we specified telephony features, such as call forwarding with MTD's, and verified these properties on an asynchronous telephony model. The compositional reasoning methods led to savings of 15%-80% in verification times, and comparable savings in space.

show abstract

Runtime Verification Past Experiences and Future Projections

Havelund

Reger

Roşu

2019

Lecture Notes in Computer Science

View full text Add to dashboard Cite

The paper provides an overview of the work performed by the authors since the year 2000 in the field of runtime verification. Runtime verification is the discipline of analyzing program/system executions using rigorous methods. The discipline covers such topics as specificationbased monitoring, where single executions are checked against formal specifications; predictive runtime analysis, where properties about a system are predicted/inferred from single (good) executions; fault protection, where monitors actively protect a running system against errors; specification mining from execution traces; visualization of execution traces; and to be fully general: computation of any interesting information from execution traces. The paper attempts to draw lessons learned from this work, and to project expectations for the future of the field.

show abstract

Events and constraints: a graphical editor for capturing logic requirements of programs

Cited by 39 publications

References 10 publications

Requirements Capture with RCAT

Requirements Capture with RCAT

Visual Specifications for Modular Reasoning about Asynchronous Systems

Runtime Verification Past Experiences and Future Projections

Contact Info

Product

Resources

About