Event propagation conditions in circuit delay computation

Abstract

Accurate and efficient computation of delays is a central problem in computer-aided design of complex VLSI circuits. Delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. Although many different propagation conditions (PCs) have been proposed for delay computation, their properties and relationships have been far from clear. We present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of detail. The most general model, called the exact or W0 model, specifies each event occurring in a circuit signal. A novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. For each waveform model, we derive the PCs that correctly capture the requirements under which an event propagates along a path. The waveform models and their PCs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. The relationships among the derived PCs and existing ones are analyzed in depth. It is proven that though many PCs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. This analysis further enables us to derive new and useful PCs. We describe such a PC, called safe static. Experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff.

Event propagation for accurate circuit delay calculation using SAT

“…Event propagation conditions for the computation of circuit delays were studied in Yalcin and Hayes [1997], where a series of waveform models were proposed to capture signal behavior at varying levels of detail. More recently, a symbolic representation of signal propagation in a circuit was presented in Mondal and Chakrabarti [2006], which could capture short-lived internal glitches in the circuit with greater accuracy.…”

Timing Analysis of Sequential Circuits Using Symbolic Event Propagation

“…The first problem of standard approaches of [6,11,13,14] relates to considering only the combinational portion of the circuit. These methods ignore sequential behavior and often overestimate the delay value.…”

“…Secondly, we observe that the delay of a circuit component (like a gate) behaves in a special way if the transitions at its inputs occur within a very short span of time (called simultaneous switching [4]) and often ignored by the most of the static timing analyzers. Thirdly, except a few methods [7,14], most timing analysis schemes consider the steady state value at the primary inputs of the combinational circuit. In synchronous sequential circuits all flip-flop outputs transit at the clock, so the assumption of single input transition [12] at the inputs may not lead to accurate results.…”

An advanced timing characterization method using mode dependency

“…These conditions are viability [5], safe static [7], static co-sensitization [3], and the Brand-Iyengar condition [1]. For lack of space, only viability is considered here.…”

“…Unfortunately, detecting false paths is difficult, and requires making use of circuit functionality. A full-fledged functional analysis, using any of the existing path propagation conditions [1][2][3]5,7], can be computationally expensive. For instance, the approach by Kukimoto and Brayton [4] can in fact detect all false paths as it calculates I/O delays accurately for each input vector.…”