Evaluation of wafer level Cu bonding for 3D integration

Kang, Sung-Geun; Kim, Youngrae; Kim, Eun‐Sol; Lim, Na-Eun; Jeong, Teakgyu; Lee, Jieun; Kim, Sarah Eunkyung; Kim, Sungdong

doi:10.1109/3dic.2012.6263014

Cited by 3 publications

(1 citation statement)

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“…However, the mismatch in the coefficient of thermal expansion (CTE) of different applied materials induces the wafer warpage during the fabrication processes. [3][4][5][6][7][8] Large wafer warpage is becoming a critical problem causing many issues such as wafer handling, lithography alignment, device reliability, etc. 9,10) The ultrathin wafers are reported to deform easily due to the increase of the elasticity/reduction of stiffness.…”

Section: Introductionmentioning

confidence: 99%

Study of wafer warpage reduction by dicing street

Feng

Shimamoto

Kawagoe³

et al. 2022

Jpn. J. Appl. Phys.

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Wafer warpage occurs during the fabrication process, which induces many issues such as wafer handling, lithography alignment, device reliability. The efficiency of dicing street on wafer warpage reduction is investigated by varying the width, depth, and pitch of dicing. With the finite element method simulation results, decreasing the dicing pitch to a quarter-pitch shows a 43.7% warpage reduction. We reveal that the method of decreasing the dicing pitch is more efficient on wafer warpage reduction than that of increasing the dicing width or depth. Furthermore, the efficiency of warpage reduction by decreasing the dicing pitch is confirmed by experiments, which shows a good agreement with the simulated results. The method of decreasing the dicing pitch cut each part smaller. These small parts deform locally instead of continually over the whole wafer, resulting in an efficient wafer warpage reduction. This research provides guidelines for chiplet design or optimization of chip size to reduce the wafer warpage.

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