Evaluation of TSV and micro-bump probing for wide I/O testing

Smith, Ken R.; Hanaway, Peter; Jolley, Mike; Gleason, Reed; Strid, E.W.; Daenen, T.; Dupas, L.; Knuts, Bruno; Marinissen, Erik Jan; Dievel, M. Van

doi:10.1109/test.2011.6139180

Cited by 51 publications

(29 citation statements)

References 8 publications

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“…Scan frequency simulations were performed on Die 0 of the FFT benchmark assuming a probe card with 100 probe needles [97]. The design contains 936 TSVs and it is assumed that TSV networks are roughly balanced, so a worse-case network of 11 TSVs was simulated.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…In [97], low-force contacts were made between probe needles and microbumps, and a worst-case contact resistance of 13 Ω was obtained. This is well within a reasonable range to achieve accurate parametric measurements for TSVs.…”

Section: Probe Equipment and The Difficulty Of Pre-bond Tsv Probingmentioning

confidence: 99%

“…Cascade Microtech Inc. has introduced a pyramid probe card that has been demonstrated at a 40 µm array pitch [97]. An illustrative example of this probe card is shown in Figure 2.2(a) with four probe needles.…”

Section: Probe Equipment and The Difficulty Of Pre-bond Tsv Probingmentioning

confidence: 99%

“…Chapter 2 and Chapter 3 described how modified boundary scan cells, called gated scan flops (GSFs), can be used along with pre-bond probing for pre-bond TSV and structural logic tests. Together, published work such as [50,97,115,116] shows that die wrappers can not only be used as a standard post-bond test interface, but also for pre-bond KGD tests. die-boundary cells is the adverse timing impact on these TSV functional paths.…”

Section: Introductionmentioning

confidence: 99%

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia

Chakrabarty

2014

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As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3DSICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge.The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through iv TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation exam...

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Probe Equipment and The Difficulty Of Pre-bond Tsv Probingmentioning

confidence: 99%

Section: Probe Equipment and The Difficulty Of Pre-bond Tsv Probingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia

Chakrabarty

2014

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“…Figure 1 shows a schematic view of the 3D-DfT architecture based on IEEE Std 1500. The architecture supports pre-bond testing through either probing the fine-pitch micro-bumps [17] or optional additional regularpitch probe pads at each die. The architecture supports mid-bond, post-bond, and final package testing by allowing elevation of test control and data up and down through the stack from the stack's external I/Os, which are typically located in the bottom die of the stack.…”

Section: Prior Work On 3d-dftmentioning

confidence: 99%

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Papameletis

Keller

Chickermane

et al. 2013

2013 18th Ieee European Test Symposium (Ets)

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Three-dimensional stacked integrated circuits (3D-SICs) implemented with through-silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller, and more energy-efficient chips. As all micro-electronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack. However, the logic dies comprising a 3D-SIC typically are complex System-on-Chip (SoC) designs that include embedded intellectual property (IP) cores, wrapped for modular test. Also, multi-tower 3D-SICs have started to emerge. In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation (EDA) tools.

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Overview of Bonding and Assembly for 3D Integration

Zhang

Ramm

2014

Handbook of 3D Integration

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Evaluation of TSV and micro-bump probing for wide I/O testing

Cited by 51 publications

References 8 publications

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Overview of Bonding and Assembly for 3D Integration

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