Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices

Johanesen, Hayley; Strauss, M.; Kenslea, Anne; Hakala, Chris; Kwakman, L.F.Tz.; Boullart, Werner; Mertens, Hans; Siew, Yong Kong; Barla, K.

doi:10.1117/12.2514995

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…Recent advances in energy dispersive spectroscopy (EDS) detectors allow composition measurements with good accuracy and precision. The technique is mainly used in presence of materials that are not easily distinguishable in STEM images [9] and to determine the presence of intermixing at the interfaces. These investigations may be hampered by overlap of different structures and materials in the TEM specimen thickness due to the 3-dimensional nature of the device with the nanowire dimensions being smaller than the thickness of a standard TEM specimen.…”

Section: Introductionmentioning

confidence: 99%

TEM investigations of gate-all-around nanowire devices

Favia

Richard

Eneman

et al. 2019

Semicond. Sci. Technol.

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Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture for ultimately scaled complementary metal oxide semiconductor devices. These are the natural evolution of the fin-shaped field effect transistor (finFET) design and enable a better electrostatic control and a higher drive current per footprint w.r.t. previous architectures. Transmission electron microscopy (TEM) analysis is employed in the development stages of these devices to investigate morphology, material diffusion, oxidation and strain in order to achieve the desired nanowires shape and size and the required performances. Nano beam diffraction and geometric phase analysis of high-resolution scanning TEM (STEM) images are used in this work to evaluate strain at the nmscale along the nanowires at different steps of the fabrication process. Initially strained Ge layers, in the early stages of the GAA NWs fabrication, relax after the fin-reveal and source/drain etching process steps. Strain is then restored after source/drain epitaxial deposition and maintained till the NWs release. TEM analyses of these structures are particularly challenging due to the dimensions of the GAA NWs which are smaller than the thickness of a typical TEM specimen. This generates artifacts due to different materials and multiple structures overlapping in projection in TEM images. To avoid these issues, several TEM lamellae at different positions in the device and/or 3D imaging STEM/energy dispersive spectroscopy tomography are employed.

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Section: Introductionmentioning

confidence: 99%

TEM investigations of gate-all-around nanowire devices

Favia

Richard

Eneman

et al. 2019

Semicond. Sci. Technol.

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Smart Automation: Machine Learning Enabled Workflow for Logic and DRAM

et al. 2021

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Current S/TEM automation requires highly trained microscopists to build specialized acquisition and analysis recipes for specific semiconductor structures. Recipes can be challenging to write and take a long time, therefore the industry continues to rely on manual operation to overcome TEM analysis demands. Time to develop robust automation is often too slow for the product change rate of industry development cycle. To overcome this barrier, Smart Automation was developed on a Thermo Scientific Metrios TM AX 200kV S/TEM as an application providing a generalized acquisition workflow that is ready to use without requiring specialist intervention. The application interacts with a Fully Convolutional Neural Network (FCN) through a user-friendly interface for navigation and auto alignments. The FCN is the key enabler for lowering the bar to automation set up with a time to robust automation within hours instead of days.

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Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices

Cited by 2 publications

References 6 publications

TEM investigations of gate-all-around nanowire devices

TEM investigations of gate-all-around nanowire devices

Smart Automation: Machine Learning Enabled Workflow for Logic and DRAM

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