Evaluation of Superjunction MOSFETs in Cascode Configuration for Hard-Switching Operation

Abstract

SuperjunctionMOSFETs in cascode configuration with low-voltage silicon MOSFETs are evaluated in this paper. The proposed structure combines the good switching performance provided by the cascode configuration with the benefits of the silicon technology such as its robustness, maturity and low-cost. This paper aims to explain and to demonstrate the reduction of switching losses of Superjunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Moreover, experimental evidence is provided using a boost converter (100 V to 400 V) operating in continuous conduction mode for different switching frequencies (100 kHz to 400 kHz) and output power levels (180 W to 500 W).

A High-Voltage Cascode-Connected Three-Level Pulse-Generator for Bio-Medical Ultrasound Applications

“…It has also previously been used in a discrete-component highvoltage pulse-generator circuit to reduce input capacitance and to achieve high transition speed [9]. Recent research [10], [11] indicates that using cascoding with discrete components in hard switching operation can even give a performance gain due to the efficient charging of the gate capacitance.…”

Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

“…As Fig. 17 shows, QOSS-HV rises with VDS-HV and achieves the 90% of the final value when the voltage is around 20 V. Since the voltage across the LV-FET is close to its breakdown voltage during the off-state [15], fixing 50 V as the output voltage of the boost converter is enough to measure most of the QOSS-HV contribution and to characterize the RR of the DUT. Note that since the highest breakdown voltage of the LV-FETs considered for the tests is 30 V (see Table II), using 50 V as output voltage ensures that the SJ-FET blocks a voltage equal or higher than 20 V. Fig.…”

“…A theoretical model of the switching mechanism during forward conduction of SJ-CCs paying especial attention to critical Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration parasitic elements can be found in [13]. Moreover, it was demonstrated that the SJ-CC can outperform the SJ-FET in standalone configuration when the switching frequency is in the order of hundreds of kHz and operating under hard-switching and high-forward current conditions [14]- [15]. Differently from the aforementioned papers, this work aims to model the third quadrant operation of the SJ-CC and to propose this configuration as a method to minimize the RR effect of the SJ-FET body-diode, enabling the use of these devices for SR [16].…”