Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore

Mikami, Hiroki; Kitaki, Shumpei; Mase, Mitsuhito; Hayashi, Akira; Shimaoka, Mamoru; Kimura, Keiji; Edahiro, Masato; Kasahara, Hironori

doi:10.1007/978-3-642-36036-7_3

Cited by 2 publications

(1 citation statement)

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“…Static task scheduling and allocation methods have been researched to satisfy the requirements of dependability and real-time performance, rather than dynamic scheduling approaches on best-effort architectures such as Network on Chips. Mikami et al [1] have proposed a power reduction method using automatic parallelizing compilers for embedded systems. Task placement and scheduling algorithms have also been thoroughly studied [2], [3], [4], [5], [6], [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems

Nakamura

Arakawa

Edahiro

2014

2014 IEEE International Conference on Cyber-Physical Systems, Networks, and Applications

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We propose in this paper a simple architecture for efficient execution of embedded control systems using a model-based design to which automatic parallelization is also applicable. This architecture makes use of the advantages of embedded control systems in the sense of parallel execution, and reduces their disadvantages by incurring minimal overhead from task scheduling and inter-task communication. With a model predictive control application, our architecture achieves communication latency 20 times faster than in current realtime OS communication methods for many cores. Moreover, our architecture achieves a speed-up for 64 cores that is 40 times that in single core execution, while its performance scalability is saturated up to 32 cores in real-time OS communication.

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