Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

Guilley, Sylvain; Sauvage, Laurent; Flament, Florent; Vong, Vinh-Nga; Hoogvorst, Philippe; Pacalet, Renaud

doi:10.1109/tc.2010.104

Cited by 33 publications

(14 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Applying DPL to the input data and key, the two wires that represent every Boolean variable have a constant toggling rate. Constant power consumption is achieved independent of the data manipulated thus making a DPA attack impossible [12] [13].…”

Section: ) Dual Rail With Precharge Logic Dplmentioning

confidence: 99%

Hardware Covert Attacks and Countermeasures

Phukan

Gebali

2016

2016 IEEE 30th International Conference on Advanced Information Networking and Applications (AINA)

View full text Add to dashboard Cite

Computing platforms deployed in many critical infrastructures, such as smart grid, financial systems, governmental organizations etc., are subjected to security attacks and potentially devastating consequences. Computing platforms often get attacked 'physically' by an intruder accessing stored information, studying the internal structure of the hardware or injecting a fault. Even if the attackers fail to gain sensitive information stored in hardware, they may be able to disrupt the hardware or deny service leading to other kinds of security failures in the system. Hardware attacks could be covert or overt, based on the awareness of the intended system. This work classifies existing hardware attacks. Focusing mainly on covert attacks, they are quantified using a proposed schema. Different countermeasure techniques are proposed to prevent such attacks.

show abstract

Section: ) Dual Rail With Precharge Logic Dplmentioning

confidence: 99%

Hardware Covert Attacks and Countermeasures

Phukan

Gebali

2016

2016 IEEE 30th International Conference on Advanced Information Networking and Applications (AINA)

View full text Add to dashboard Cite

show abstract

“…Moreover, there are circuit-level techniques where dual-rail or multi-rail encoding of data are used [23]. They are dedicated to reduce current variations when the loads of all rails are balanced.…”

Section: A 32-bit Lacsl Montgomery Multipliermentioning

confidence: 99%

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier

Chen

Tisserand

Popovici

et al. 2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

View full text Add to dashboard Cite

Abstract-A significant number of cryptographic architectures rely on the efficient and resilient implementation of the Montgomery modular multiplier. One of the most used attacks on cryptographic implementations is based on Differential Power Analysis (DPA) or one of its variants. In this paper, a specially adjusted Latch-less Asynchronous Charge Sharing Logic (LACSL) is developed to inherently defend such architecture against DPA attacks. The proposed logic provides input data independent low-power/energy consumption which is attributed to interleaved charge sharing stages with non-static elements involved in the data path. A 32-bit LACSL Montgomery Multiplier (case study) is extensively tested through HSPICE simulations and great consistency in power/energy consumption is achieved. The normalized energy deviation and normalized standard deviation are only 0.048 and 0.011, respectively. Compared with the original ACSL implementation, besides the impressive energy coherence, 42% energy saving is demonstrated plus that the leakage power is 3.5 times smaller. Furthermore, the scalability of the proposed multiplier is explored where 64-bit, 128-bit and 256-bit designs are implemented. Again, great energy consistency is found with the highest deviation being 0.5%. The proposed techniques can be easily migrated to other low-power circuits for which accurate power/energy models can be built, independent of the input data profile.

show abstract

“…We notice that those alternative "DPL without EPE" logics yield similar performances: DRSL [18] 6 , iMDPL [65], IWDDL [52], STTL [75], [76], SecLib [35], [32], [33], [36], WDDL w/o EPE [11], [12], BCDL [60], [20] and LBDL [89].…”

Section: Cost Estimation Of Fir Versus Traditional Approachesmentioning

confidence: 99%

Fault Injection Resilience

Guilley

Sauvage

Danger

et al. 2010

2010 Workshop on Fault Diagnosis and Tolerance in Cryptography

Self Cite

View full text Add to dashboard Cite

Abstract-Fault injections constitute a major threat to the security of embedded systems. Errors occurring in the cryptographic algorithms have been shown to be extremely dangerous, since powerful attacks can exploit few of them to recover the full secrets. Most of the resistance techniques to perturbation attacks have relied so far on the detection of faults. We present in this paper another strategy, based on the resilience against fault attacks. The core idea is to allow an erroneous result to be outputted, but with the assurance that this faulty information conveys no information about the secrets concealed in the chip. We first underline the benefits of FIR: false positive are never raised, secrets are not erased uselessly in case of uncompromising faults injections, which increases the card lifespan if the fault is natural and not malevolent, and FIR enables a high potential of resistance even in the context of multiple faults. Then we illustrate two families of fault injection resilience (FIR) schemes suitable for symmetric encryption. The first family is a protocollevel scheme that can be formally proved resilient. The second family mobilizes a special logic-level architecture of the cryptographic module. We notably detail how a countermeasure of this later family, namely dual-rail with precharge logic style, can both protect both against active and passive attacks, thereby bringing a combined global protection of the device. The cost of this logic is evaluated as lower than detection schemes. Finally, we also give some ideas about the modalities of adjunction of FIR to some certification schemes.

show abstract

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

Cited by 33 publications

References 29 publications

Hardware Covert Attacks and Countermeasures

Hardware Covert Attacks and Countermeasures

Asynchronous Charge Sharing Power Consistent Montgomery Multiplier

Fault Injection Resilience

Contact Info

Product

Resources

About