Evaluation of interval-based dynamic voltage scaling algorithms on mobile Linux system

Kimm, Haklin; Shin, Sung Y.; Sung, Chang Oan

doi:10.1145/1244002.1244251

Cited by 3 publications

(7 citation statements)

References 7 publications

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“…Past research have found that the power consumed by a CPU during operation is linear to the CPU clock frequency [1], [5], [6]. Simulation based power measurement prediction assumes that the CPU power consumption is calculated as the cube of frequency, which do not take into account the processor's idle power requirement [1].…”

Section: Power Estimation and Predictionmentioning

confidence: 99%

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The effects of CPU load & idle state on embedded processor energy usage

Daud

Ahmad

Lynn

et al. 2014

2014 2nd International Conference on Electronic Design (ICED)

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Device power consumption is a serious design consideration especially for embedded systems. By reducing the power consumption of a particular system, we could effectively prolong the runtime of the system, allowing for longer operational condition of a particular system. Previous studies have suggested that the power characteristics of a modern embedded processor have since been improved with manufacturer's implementation of better energy-focused designs. Implementation of hardware optimization such as better clock and power gating have been shown to produce better energy usage during on-load and off-load processing.In this paper we benchmarked the energy use of a modern embedded processor and study the effects of idling time to the processor and system energy usage. We have found that the processor energy use is significantly reduced in the instant that the processor goes idle during the execution process. The idling time during a processing timeslice allows the processor to use significantly less energy without explicitly depending on a frequency scaling algorithm to reduce energy consumption. This power saving feature directly implemented inside the processor hardware have the possibility to render software based frequency scaling algorithm and DVFS method to be less effective in reducing energy usage.

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Section: Power Estimation and Predictionmentioning

confidence: 99%

“…According to the equation, reduction in the clock frequency will greatly affect the active power. Another generally used equation to predict CPU power consumption comes in the form of CMOS power usage equation [6], [7], [8], [9], [10], [11]. The equation is given below:…”

Section: Power Estimation and Predictionmentioning

confidence: 99%

The effects of CPU load & idle state on embedded processor energy usage

Daud

Ahmad

Lynn

et al. 2014

2014 2nd International Conference on Electronic Design (ICED)

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“…Such a technology is particularly beneficial for embedded systems mainly because of the power constraints and heat dissipation reduction that allow for better use of the available power [4]. The concept of reduced power consumption in an embedded system especially battery power devices are categorized as more important than their fixed power system with access to wall power [1].…”

Section: Dynamic Voltage and Frequency Scalingmentioning

confidence: 99%

“…Linux is fast becoming a major player in the embedded devices platform. With projections from research firms suggesting that shipping of Internet connected devices and Internet of Things (IOT) embedded devices surpassing the shipment of personal computers and smartphones, it is more imperative that maximum energy efficiency are extracted from the devices so that operational time of the devices are prolonged [1].…”

Section: Introductionmentioning

confidence: 99%

The Effects of Various Frequency Scaling Algorithm on Embedded Linux CPU Power Consumption

Daud

Ahmad

Lynn

2014

IJCT

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In this paper we have tested various frequency scaling algorithm available in Linux and measured the effects of the different algorithms during operation in an actual system. We have tested all the default scaling algorithms included in Linux in a controlled testing environment and measured the actual effects of the scaling algorithms to the CPU power consumption during operation. In order to retain high accuracy and avoid unnecessary components from affecting the results, we have conducted the measurement directly on the CPU power supply line and logged the power usage in real time.

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“…Most previous work in this area has focused on the use of techniques like gating [1,28,16,11], voltage and frequency scaling [27,14,22,2,26,32,19,29,39], or heterogeneity [13,23] to reduce processor power consumption. These approaches usually target average power dissipation for uniprocessors or chip multiprocessor architectures with a small number of cores.…”

Section: Related Workmentioning

confidence: 99%

Three scalable approaches to improving many-core throughput for a given peak power budget

Sartori

Kumar

2009

2009 International Conference on High Performance Computing (HiPC)

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Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states. These techniques suffer from two limitations. First, they do not prevent instantaneous power from exceeding the peak power budget, but instead trigger corrective action when the budget has been exceeded. Second, while these techniques may work for multi-core architectures (processors with small number of cores), they are not suitable for many-core architectures (processors with tens or possibly hundreds of cores on the same die) due to an exponential explosion in the number of global power management states.In this paper, we look at three scalable techniques for peak power management for many-core architectures. The proposed techniques (mapping the power management problem to a knapsack problem, mapping it to a genetic search problem, and mapping it to a simple learning problem with confidence counters) prevent power from exceeding the peak power budget and enable the placement of several more cores on a die than what the power budget would normally allow. We show up to 47% (33% on average) improvements in throughput for a given power budget. Our techniques outperform the static oracle by 22%.

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Evaluation of interval-based dynamic voltage scaling algorithms on mobile Linux system

Cited by 3 publications

References 7 publications

The effects of CPU load & idle state on embedded processor energy usage

The effects of CPU load & idle state on embedded processor energy usage

The Effects of Various Frequency Scaling Algorithm on Embedded Linux CPU Power Consumption

Three scalable approaches to improving many-core throughput for a given peak power budget

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