Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Wu, Tse-Ching; Chen, Chien-Ju; Chen, Yin-Nien; Hu, Vita Pi‐Ho; Su, Pin; Chuang, Ching-Te

doi:10.1109/socc.2015.7406978

Cited by 5 publications

(3 citation statements)

References 16 publications

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“…The main conduction mechanism of this device is determined by the band-to-band tunneling at the source-channel; therefore, the SS of the TFET is able to achieve a high-efficiency ultra-lowvoltage computation due to a sub-60-mv/dec operation [21][22][23][24][25]. The lower SS of the TFET produces a relatively large on-current at a lower supply voltage, a reduced leakage, and an enhanced low-voltage, as a result of thermionic emission not being involved in this device [26][27][28]. The TFET is based on III-V heterojunction structures which produces an asymmetric device with a unidirectional current, and is the cause of the p-type TFET having an on-current four times smaller than its n-type counterpart [21,23].…”

Section: Introductionmentioning

confidence: 99%

“…The TFET is based on III-V heterojunction structures which produces an asymmetric device with a unidirectional current, and is the cause of the p-type TFET having an on-current four times smaller than its n-type counterpart [21,23]. In addition, the large capacitance of the TFET caused by its source-channel barrier induces voltage spikes during circuit switching, which can increase power consumption [23,26].…”

Section: Introductionmentioning

confidence: 99%

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Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

et al. 2022

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Miniaturization and portable devices have reshaped the electronic device landscape, emphasizing the importance of high performance while maintaining energy efficiency to ensure long battery life. FinFET and Tunnel-FET technologies have emerged as attractive alternatives to overcome the limitations of supply voltage scaling for ultra-low power applications. This work compares the performance of 10 nm FinFET- and TFET-based digital circuits from basic logic gates up to an 8k gates low-power microprocessor. When compared with their FinFET-based counterparts, the TFET-based logic gates have lower leakage power when operated below 300 mV, show higher input capacitance, and exhibit a reduced propagation delay under different fan-in and fan-out conditions. Our comparative study was extended to the synthesis of an MSP-430 microprocessor through standard cell libraries built particularly for this work. It is demonstrated that the TFET-based synthesized circuits operating at ultra-low voltages achieve a higher performance in terms of speed at the cost of increased power consumption. When the speed requirements are relaxed, the TFET-based designs are the most energy-efficient alternative. It is concluded that the TFET is an optimal solution for ultra-low voltage design.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

et al. 2022

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“…It is therefore critical to develop circuits capable of performing complex tasks under stringent energy constraints. Various lowpower digital design techniques have been explored over the past several decades, but supply voltage scaling is generally shown to be the most effective technique due to the quadratic dependence of dynamic energy on the supply voltage [1]. References [2] and [3] have shown that minimum energy is typically achieved when transistors operate in the subthreshold region by working with a V DD scaled below V th .…”

Section: Introductionmentioning

confidence: 99%

Assessment of 10 nm Tunnel- FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Rendon

Cao

Landázuri

et al. 2021

2021 IEEE Fifth Ecuador Technical Chapters Meeting (ETCM)

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The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 mV. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.

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TFET and FinFET Hybrid Technologies for SRAM Cell: Performance Improvement over a Large VDD-Range

Liautard

Trojman

Arevalo

et al. 2019

2019 IEEE Fourth Ecuador Technical Chapters Meeting (ETCM)

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Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications

Cited by 5 publications

References 16 publications

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

Assessment of 10 nm Tunnel- FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

TFET and FinFET Hybrid Technologies for SRAM Cell: Performance Improvement over a Large VDD-Range

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