Evaluation of Booth encoding techniques for parallel multiplier implementation

Energy delay analysis of partial product reduction methods for parallel multiplier implementation

“…For parallel multipliers using radix 4 MBA, the number of partial products are reduced to n/2 for an nXn 2's complement multiplication. This same task can be accomplished by the use of 4:2 compressors [3] also, as proposed by D. Villeger et al [4]. The authors in [4] have shown that 4:2 compressors can reduce the number of partial products to n/2 in less time and using fewer gates compared to radix 4 MBA while C. Nagendra et al [5] also arrived at similar results.…”

“…This same task can be accomplished by the use of 4:2 compressors [3] also, as proposed by D. Villeger et al [4]. The authors in [4] have shown that 4:2 compressors can reduce the number of partial products to n/2 in less time and using fewer gates compared to radix 4 MBA while C. Nagendra et al [5] also arrived at similar results. Norio Ohkubo et al [6] acknowledged the equivalence of partial product generation using MBA and 4:2 compressors, though they favored partial product generation using the MBA scheme owing to the area advantage offered by such a scheme.…”

Multiplier structures for low power applications in deep-CMOS

“…In [10], the authors showed that Booth encoding provides energy reduction at the relaxed delay targets. As the delay target is getting stricter, Non-Booth multipliers become a more energyefficient structure [10,11]. After the partial product generation block, the partial products will be reduced to two rows, a row of sum and a row of carry signals.…”

Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic

“…Booth encoder is employed for efficient generation of partial products [2]. The Partial products generated are either Multiplicand ( The final module of the multiplier is Wallace tree adder.…”