Evaluation of a Floating-Point Intensive Kernel on FPGA

Jin, Zheming; Finkel, Hal; Yoshii, Kazutomo; Cappello, Franck

doi:10.1007/978-3-319-75178-8_53

Cited by 9 publications

(3 citation statements)

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“…As future works we plan to further investigate the performance and energy-efficiency of this device, producing different empirical Roofline plots for different FPGA clock frequencies. We will also try to increase the double-precision performance, initially trying newer versions of the Xilinx Vivado tools, since the floating-point IP Core seems to be improved in the last months and also specialized implementations for FMA operations seems now to be available 7 . We also plan to experiment software techniques, such as the use of extended-precision [19], evaluating its performance, energy-efficiency and usability for actual HPC scientific applications, wrt regular double-precision.…”

Section: Discussionmentioning

confidence: 99%

“…These new programming possibilities, in conjunction with the high intrinsic hardware parallelism, and an increased amount of computing resources and DSPs for floatingpoint operations [6,7], are increasing the interest towards their usage as accelerators in HPC installations [6]. A great interest in FPGAs, in the HPC context, is also towards their possible high energy-efficiency -thanks to their intrinsic parallelism and low clock frequencies -wrt ordinary processors, and also GPUs for some applications [8].…”

Section: Introductionmentioning

confidence: 99%

“…We would measure the same performance executing a generic sequence of additions and multiplications 7. https://www.xilinx.com/support/documentation/ip_documentation/ru/floatingpoint.html#zynquplus E. Calore and S.F.…”

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confidence: 99%

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Energy-Efficiency Evaluation of FPGAs for Floating-Point Intensive Workloads

Calore

Schifano

2020

Parallel Computing: Technology Trends

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In this work we describe a method to measure the computing performance and energy-efficiency to be expected of an FPGA device. The motivation of this work is given by their possible usage as accelerators in the context of floating-point intensive HPC workloads. In fact, FPGA devices in the past were not considered an efficient option to address floating-point intensive computations, but more recently, with the advent of dedicated DSP units and the increased amount of resources in each chip, the interest towards these devices raised. Another obstacle to a wide adoption of FPGAs in the HPC field has been the low level hardware knowledge commonly required to program them, using Hardware Description Languages (HDLs). Also this issue has been recently mitigated by the introduction of higher level programming framework, adopting so called High Level Synthesis approaches, reducing the development time and shortening the gap between the skills required to program FPGAs wrt the skills commonly owned by HPC software developers. In this work we apply the proposed method to estimate the maximum floating-point performance and energy-efficiency of the FPGA embedded in a Xilinx Zynq Ultrascale+ MPSoC hosted on a Trenz board.

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Section: Discussionmentioning

confidence: 99%