Abstract:In this paper, we investigate the hybrid TFET-FinFET 32-bit carry-look-ahead adder (CLA) circuit and compare the delay, power and power-delay product (PDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. In the hybrid design, TFETs are used for the top critical path to reduce the longest path delay… Show more
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