Evaluating the Numerical Stability of Posit Arithmetic

Buoncristiani, Nicholas; Shah, Sanjana; Donofrio, David; Shalf, John

doi:10.1109/ipdps47924.2020.00069

Cited by 11 publications

(11 citation statements)

References 11 publications

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“…The factor 𝑢 is defined as 𝑢 = 2 2 𝑒s . The POSIT format is identified as Posit(𝑛 bit , 𝑒 s ) according to [2], where 𝑛 bit is the total bit length of a variable in the Posit format. Only the 32-bit POSIT format is considered in this work; hence, we use Posit(32,2) and set 𝑒 s = 2 and 𝑢 = 2 2 2 = 16.…”

Section: Posit Arithmeticmentioning

confidence: 99%

“…Our work builds upon these works by implementing an accelerator for POSIT arithmetic that specifically targets linear algebra operations, such as matrix-matrix multiplication. Additionally, our work is complementary to [2], in which POSIT arithmetic was applied to the Conjugate Gradient method and Cholesky decomposition for sparse matrices as iterative solvers. In this study, we directly compare the performance of our FPGA designs with our GPU implementation by solving two decomposition algorithms for dense matrices: Cholesky and LU decompositions.…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of POSIT Arithmetic with Accelerators

Nakasato,

Murakami,

Kono

et al. 2024

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region

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We present an evaluation of 32-bit POSIT arithmetic through its implementation as accelerators on FPGAs and GPUs. POSIT, a floating-point number format, adaptively changes the size of its fractional part. We developed hardware designs for FPGAs and software for GPUs to accelerate linear algebra operations using Posit(32,2) arithmetic. Our FPGA-and GPU-based accelerators in Posit(32,2) arithmetic significantly accelerated the Cholesky and LU decomposition algorithms for dense matrices. In terms of numerical accuracy, Posit(32,2) arithmetic is approximately 0.5 -1.0 digits more accurate than the standard 32-bit format, especially when the norm of the elements of the input matrix is close to 1. Evaluating power consumption, we observed that the power efficiency of the accelerators ranged between 0.043 -0.076 Gflops/watts for the LU decomposition in Posit(32,2) arithmetic. The power efficiency of the latest GPUs as accelerators of Posit(32,2) arithmetic is better than that of the evaluated FPGA chip.

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Section: Posit Arithmeticmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evaluation of POSIT Arithmetic with Accelerators

Nakasato,

Murakami,

Kono

et al. 2024

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region

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“…The Posit system [4], [12] is a tapered system proposed in 2017 as a drop-in alternative to the widely adopted IEEE-754-1985 Standard for Floating-Point Arithmetic [13] and its 2008 revision [14]. The Posit/Unum system has since been studied for its potential in low-precision deep learning applications (AI on the edge) [15], [16], for numerical and scientific applications [17], [18], and its hardware costs have been studied [19], [20]. The Posit system can be viewed as a tapered floating point system that expresses the most significant part of the exponent in signed base 1, rather than base 2.…”

Section: Introductionmentioning

confidence: 99%

“…The Posit system offers enhanced best-case precision and potentially enhanced dynamic range relative to the fixedexponent size IEEE-754 system. A recent independent study [17] finds that, if inputs are scaled to take advantage of the optimal range for the Posit system, the results are numerically superior to equally-sized IEEE-754 floats.…”

Section: Introductionmentioning

confidence: 99%

A Tapered Floating Point Extension for the Redundant Signed Radix 2 System Using the Canonical Recoding

Schoenbaum¹

2021

Preprint

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A tapered floating point encoding is proposed which uses the redundant signed radix 2 system and is based on the canonical recoding. By making use of ternary technology, the encoding has a dynamic range exceeding that of the IEEE 754-1985 Standard for Floating Point Arithmetic (IEEE-754-1985, and precision equal to or better than that of the IEEE-754-1985 system and the recently proposed Posit system when equal input sizes are compared. In addition, the encoding is capable of supporting several proposed extensions, including extensions to integers, boolean values, complex numbers, higher number systems, low-dimensional vectors, and system artifacts such as machine instructions. A detailed analytic comparison is provided between the proposed encoding, the IEEE-754-1985 system, and the recently proposed Posit number system.

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“…There is a variety of previous works implementing arithmetic-logic units (ALUs) [33] [4] [59] and bare arithmetic data paths [8] [67] [60] for alternative formats, and comparing their area requirements to IEEE-754 units. In addition, some studies have analyzed the numerical stability of the Posit and the Bfloat16 arithmetics with respect to IEEE-754 [12] [7]. Despite this extensive amount of work, there are no approaches considering the area, performance, power, and accuracy tradeoffs of these alternative computer number formats in the context of a real system implementing them.…”

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confidence: 99%