Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA Designs

Abstract

Reduced Precision Redundancy (RPR) is an alternative to Triple Modular Redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multi-stage circuits and analyze the error mitigation tradeoffs. As case study, several Fast Fourier Transform designs were tested with low energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach. This chapter has been published as an article: [4]