Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores

Gutierrez, Anthony; Dreslinski, Ronald G.; Mudge, Trevor

doi:10.1109/samos.2014.6893211

Cited by 4 publications

(2 citation statements)

References 22 publications

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“…e rst case worth analysing is when cores have private caches and share no components except the main memory (Figure 2a). is sharing scheme is a common setup in chip multiprocessors and HMPs, with numerous industrial and academic examples [1,6,16]. Here every migration causes the system to transfer it's register le from the retiring to the incoming core before resuming normal operation.…”

Section: Heterogeneous Multiprocessor Organizationmentioning

confidence: 99%

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Nucleus

Vougioukas

Sandberg

Diestelhorst

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Heterogeneous multi-processors are designed to bridge the gap between performance and energy e ciency in modern embedded systems. is is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best se ing for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance. We develop a simulation methodology that can 1) isolate the hardware e ects of migrations from the so ware, 2) directly compare the performance of di erent core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with li le performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside bu er that matches performance and e ciency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance bene ts without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without a ecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or be er system operation without having to aggressively share the entire memory system or to revert to migration periods ner than 100k instructions. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permi ed. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. Instructions per cycle Fig. 1. An excerpt of execution of dijkstra running on two di erent core types. Sampling at a higher resolution reveals phases that can potentially be exploited to increase e iciency. INTRODUCTIONIn today's embedded devices, performance is always tied to power constraints and energy e ciency. is happens because, while process technology scaling is enabling larger transistor densities, power per area has shown to increase beyond a certain thr...

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Section: Heterogeneous Multiprocessor Organizationmentioning

confidence: 99%

“…Some studies have explored the notion of migrating execution amongst heterogeneous cores that takes into account the e ect of the memory system [9] [16]. Improvement is limited to relatively coarse-grained switching frequencies and modi cations are required for the system to achieve them.…”

Section: Related Workmentioning

confidence: 99%

Nucleus

Vougioukas

Sandberg

Diestelhorst

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Fast and Scalable Thread Migration for Multi-core Architectures

Rodrigues¹,

Roma

Pfister

2015

2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing

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A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

Mittal

2016

ACM Comput. Surv.

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To meet the needs of a diverse range of workloads, asymmetric multicore processors (AMPs) have been proposed, which feature cores of different microarchitecture or ISAs. However, given the diversity inherent in their design and application scenarios, several challenges need to be addressed to effectively architect AMPs and leverage their potential in optimizing both sequential and parallel performance. Several recent techniques address these challenges. In this article, we present a survey of architectural and system-level techniques proposed for designing and managing AMPs. By classifying the techniques on several key characteristics, we underscore their similarities and differences. We clarify the terminology used in this research field and identify challenges that are worthy of future investigation. We hope that more than just synthesizing the existing work on AMPs, the contribution of this survey will be to spark novel ideas for architecting future AMPs that can make a definite impact on the landscape of next-generation computing systems.

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Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores

Cited by 4 publications

References 22 publications

Nucleus

Nucleus

Fast and Scalable Thread Migration for Multi-core Architectures

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

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