Evaluating Emerging CXL-enabled Memory Pooling for HPC Systems

Wahlgren, Jacob; Gokhale, Maya

doi:10.1109/mchpc56545.2022.00007

Cited by 10 publications

(3 citation statements)

References 23 publications

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“…16,[18][19][20][21] Jacob et al developed an emulator to evaluate a memory subsystem design leveraging CXL-enabled memory pooling and demonstrated that a disaggregated memory system can effectively support bandwidth-intensive unstructured mesh-based applications like OpenFOAM. 22 Debendra discussed the potential and limitations of using CXL to build composable and scale-out systems spanning the rack through the pod at the data center. 23 Furthermore, many studies focus on efficient memory management, 16,[24][25][26] as the implementation of memory disaggregation typically involves a concern about bandwidth and latency penalties over the network, which may adversely affect application performance.…”

Section: Related Workmentioning

confidence: 99%

“…Wang et al developed Canvas to improve the slowdown by applications co‐running on the remote memory, 17 as well as other work on fast data swap between compute nodes and remote memory nodes 16,18–21 . Jacob et al developed an emulator to evaluate a memory subsystem design leveraging CXL‐enabled memory pooling and demonstrated that a disaggregated memory system can effectively support bandwidth‐intensive unstructured mesh‐based applications like OpenFOAM 22 . Debendra discussed the potential and limitations of using CXL to build composable and scale‐out systems spanning the rack through the pod at the data center 23 .…”

Section: Related Workmentioning

confidence: 99%

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Evaluating the potential of disaggregated memory systems for HPC applications

Ding,

Maris,

Nam

et al. 2024

Concurrency and Computation

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SummaryDisaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such systems to improve overall system memory utilization, but performance can vary across workloads. High‐performance computing (HPC) is crucial in scientific and engineering applications, where HPC machines also face the issue of underutilized memory. As a result, improving system memory utilization while understanding workload performance is essential for HPC operators. Therefore, learning the potential of a disaggregated memory system before deployment is a critical step. This paper proposes a methodology for exploring the design space of a disaggregated memory system. It incorporates key metrics that affect performance on disaggregated memory systems: memory capacity, local and remote memory access ratio, injection bandwidth, and bisection bandwidth, providing an intuitive approach to guide machine configurations based on technology trends and workload characteristics. We apply our methodology to analyze thirteen diverse workloads, including AI training, data analysis, genomics, protein, fusion, atomic nuclei, and traditional HPC bookends. Our methodology demonstrates the ability to comprehend the potential and pitfalls of a disaggregated memory system and provides motivation for machine configurations. Our results show that eleven of our thirteen applications can leverage injection bandwidth disaggregated memory without affecting performance, while one pays a rack bisection bandwidth penalty and two pay the system‐wide bisection bandwidth penalty. In addition, we also show that intra‐rack memory disaggregation would meet the application's memory requirement and provide enough remote memory bandwidth.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Evaluating the potential of disaggregated memory systems for HPC applications

Ding,

Maris,

Nam

et al. 2024

Concurrency and Computation

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“…CXL analysis and evaluation: CXL is an emerging standard that is attracting attention not only from industry but also from research communities. Analysis and evaluation of CXL-enabled systems are being conducted ranging from memory pooling in general [12,23,41,44,46], to more specific applications such as machine learning [19] and in-memory databases [21]. CXL studies involving accelerators such as GPU and FPGA are appearing [3,19].…”

Section: Related Workmentioning

confidence: 99%

GPU Graph Processing on CXL-Based Microsecond-Latency External Memory

Sano,

Bando,

Hiwada

et al. 2023

Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analys

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In GPU graph analytics, the use of external memory such as the host DRAM and solid-state drives is a cost-effective approach to processing large graphs beyond the capacity of the GPU onboard memory. This paper studies the use of Compute Express Link (CXL) memory as alternative external memory for GPU graph processing in order to see if this emerging memory expansion technology enables graph processing that is as fast as using the host DRAM. Through analysis and evaluation using FPGA prototypes, we show that representative GPU graph traversal algorithms involving finegrained random access can tolerate an external memory latency of up to a few microseconds introduced by the CXL interface as well as by the underlying memory devices. This insight indicates that microsecond-latency flash memory may be used as CXL memory devices to realize even more cost-effective GPU graph processing while still achieving performance close to using the host DRAM. CCS CONCEPTS• Hardware → Analysis and design of emerging devices and systems; Memory and dense storage.

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