EVAL: Utilizing processors with variation-induced timing errors

Abstract

Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case parameter values, we may lose substantial performance. An alternate approach explored in this paper is to design for closer to nominal values, and provide some transistor budget to tolerate unavoidable variationinduced errors.To assess this approach, this paper first presents a novel framework that shows how microarchitecture techniques can trade off variation-induced errors for power and processor frequency. Then, the paper introduces an effective technique to maximize performance and minimize power in the presence of variationinduced errors, namely High-Dimensional dynamic adaptation. For efficiency, the technique is implemented using a machinelearning algorithm. The results show that our best configuration increases processor frequency by 56% on average, allowing the processor to cycle 21% faster than without variation. Processor performance increases by 40% on average, resulting in a performance that is 14% higher than without variation -at only a 10.6% area cost.

Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications

“…The proposed solution works in a conservative manner that guarantees "always correct" computation and timing correctness of the circuit with respect to the delayed clock edge, even in the worst-case scenario. [26], Blueshift [27] Razor [12], DSTB, TDTB [14], TIMBER [17], soft edge flip-flop [16] SlackOptimizer, SkewOptimizer, CombOpt [29] Retiming [21], skew scheduling [23], gate sizing [24] Proposed SBFF + logic downsizing [27] Razor [12], DSTB, TDTB [14], TIMBER [17], soft edge flip-flop [16] SlackOptimizer, SkewOptimizer, CombOpt [29] Retiming [21], skew scheduling [23], gate sizing [24] Proposed SBFF + logic downsizing The proposed approach, which is an extension of our previous work [35], leverages the underutilized slack present in processor pipelines after the tool-based optimizations. We use Static Timing Analysis (STA) to look for near critical endpoints with sufficient consecutive slack after placement and logic optimizations.…”

Efficient parameter variation sampling for architecture simulations

“…In this paper, we apply this to evaluate two important architecturally relevant component properties that are strong functions of parameter variation: timing error rate P e and leakage power P leak . In an era where architects are considering timing speculation as a way to improve performance and efficiency, timing error rates are important properties of a design [2], [3], [13]. In deep submicron technology, leakage power comprises a significant portion of total chip power and therefore serves as an essential design characteristic.…”

“…EVALUATION Our Quasi-Monte Carlo and Multi-Resolution variation models are suitable for examining the impact of parameter variation on many aspects of a microarchitecture. In this section, we evaluate our variation model and sampling methodology by applying it to two aspects of high-performance processor design which are extremely sensitive to parameter variation: (1) timing errors associated with timing speculative architectures [2] and (2) chip leakage power. Our first application examines trade-offs in observed timing errors versus clock frequency and compares convergence rates of timing error rates under low-discrepancy sequences versus standard Monte Carlo samples.…”

“…In the second application, we examine the on-die leakage power variations with both SR-LD sampling and MR-LD sampling comparing to MC. Both applications are compared against VARIUS [1] Monte Carlo samples as a baseline case, which has been widely adaped for architectural parameter variation sampling [2], [4].…”

“…In the realm of architecture, each Monte Carlo simulation would require running a detailed architecture simulator for anywhere from one hundred million to one billion instructions -a task which may take hours. Given that most recent studies in the architecture community may incorporate ten or more individual benchmark programs [2]- [4], the full set of Monte Carlo simulations may require thousands of compute-hours.…”