EUVL defect printability: an industry challenge

Kwon, Hyun‐Han; Teki, Ranganath; Harris-Jones, Jenah; Cordes, Aaron

doi:10.1117/12.923013

Cited by 2 publications

(3 citation statements)

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“…7,8 Figure 10 shows the dimensions of native ML phase defects and the characteristics of defect decoration. Most native ML phase defects captured by inspection tools are large enough to be classified as printable defects.…”

Section: Dps For Native ML Phase Defectsmentioning

confidence: 99%

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EUV mask multilayer defects and their printability under different multilayer deposition conditions

Kwon¹,

Harris-Jones²,

Cordes³

et al. 2012

SPIE Proceedings

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Extreme ultraviolet (EUV) patterning appears feasible using currently available EUV exposure tools, but some issues must still be resolved for EUV patterning to be used in production. Defects in EUV mask blanks are one such major issue and inspection tools are needed to detect phase defects on EUV mask blanks that could possibly print on the wafer. Currently available inspection tools can capture defects on the mask, but they also need to be able to classify possible printable defects. Defect classification for repair and mitigation of printable defects is very difficult using deep ultraviolet (DUV) inspection tools; however, if the actinic inspection tool (AIT) could gather defect information from more multilayer (ML) stacks, it may be able to separate printable defects from unprintable defects. If unprintable defects could be eliminated, the defect information could be used for mask pattern shifts to reduce printable defects. Fewer defects would need to be repaired if there were a better chance of capturing printable defects using an actinic inspection tool. Being able to detect printable defects on EUV blanks is therefore critical in mask making.In this paper, we describe the characterization of programmed ML phase defects in the manufacturing of EUV mask blanks using the state-of-the-art mask metrology equipment in SEMATECH's Mask Blank Development Center (MBDC). Programmed defects of various dimensions were prepared using e-beam patterning technology and Mo/Si MLs were deposited with SEMATECH's best known method (BKM) and pit smoothing conditions on programmed defects to characterize ML phase defects. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) were used to study ML profile changes, while SEMATECH's AIT was used to image ML phase defects and predict their printability. Multilayer defect reconstruction (MDR) was done using AFM images, which were then compared to TEM images. Defect printability simulation (DPS) was used for comparison to AIT through-focus images. 22 nm, 27 nm, and 32 nm line and space (L/S) absorber patterns were positioned on top of programmed ML phase defects and simulated defect printability. The ML phase defects are located at the edge of L/S patterns and at the center of space patterns and Bossung plot was used to separate printable defects from unprintable defects.

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Section: Dps For Native ML Phase Defectsmentioning

confidence: 99%

“…Because defects in EUV mask blanks are one such major issue, much research is focusing on defect printability. [1][2][3][4][5][6][7] Absorber defects, which can be detected as clear and opaque defects and particles, are common to conventional optical masks. However, EUV masks have ML phase defects that must be classified.…”

Section: Introductionmentioning

confidence: 99%

EUV mask multilayer defects and their printability under different multilayer deposition conditions

Kwon¹,

Harris-Jones²,

Cordes³

et al. 2012

SPIE Proceedings

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“…These values are typical defect sizes currently being reported, as illustrated in [34]. We show results with different number of defects on the mask to highlight 4 All dimensions in this section are mask scale unless explicitly stated mask defectivity levels that are acceptable after floorplanning.…”

Section: A Setupmentioning

confidence: 99%

Design-Aware Defect-Avoidance Floorplanning of EUV Masks

Kagalwalla

Gupta

2013

IEEE Trans. Semicond. Manufact.

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Abstract-Fabricating defect-free mask blanks remains a major obstacle for the adoption of EUV lithography. We propose a simulated annealing based gridded floorplanner for single project, multiple die reticles that minimizes the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 60-defect mask, our approach can improve the mask yield from 0% to 26%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield to 99.6%. These improvements are achieved with a limited area overhead of less than 0.2% on the exposure field. Our simulation results also indicate that around 10%−30% mask yield improvement is possible as a result of floorplanning compared to shifting the entire mask pattern. Our floorplanner can tolerate a defect position error (due to mask blank inspection tools) of 0.25µm with just a 2% reduction in yield. The impact of defect dimensions and multi-layer EUV patterning on the viability of floorplanning is also analyzed in this work.

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EUVL defect printability: an industry challenge

Cited by 2 publications

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EUV mask multilayer defects and their printability under different multilayer deposition conditions

EUV mask multilayer defects and their printability under different multilayer deposition conditions

Design-Aware Defect-Avoidance Floorplanning of EUV Masks

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