EUV mask synthesis with rigorous ILT for process window improvement

Braam, Kyle; Selinidis, Kosta; Hoppe, W; Cai, Hao; Xiao, Gao

doi:10.1117/12.2515156

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…The level-set optimization of a particular cost function is calculated by simulating the mask obtained by the zero level set. ILT uses a variety of different cost functions to drive the optimization in order to satisfy different simulator conditions such as nominal convergence, improved process window, MEEF, and/or controlling SRAF printing [10]- [11]. These cost functions are tailored with special topology markers ("topos" or feature markers) and specific weights (Figure 4).…”

Section: Ilt Mask Optimizationmentioning

confidence: 99%

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Digaum¹,

Chiang

Wang

et al. 2023

DTCO and Computational Patterning II

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In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.

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Section: Ilt Mask Optimizationmentioning

confidence: 99%

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Digaum¹,

Chiang

Wang

et al. 2023

DTCO and Computational Patterning II

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“…However, today all EDA companies that offer OPC products also offer ILT products of some kind, some used for fixing hotspots like Synopsys, 19,20,98 some for model-based SRAF generation like ASML Brion. [99][100][101] ILT was extended to EUV by Synopsys [102][103][104][105] and ASML Brion started exploring using deep learning (DL) in ILT for SRAF generation. [99][100][101] Despite steady, continuing research and development across academia and industry through the decade and demonstration of the use of ILT to correct full-chip designs, ILT was still seen as an advanced method for use in critical hotspots, rather than as a technique to be applied to full-chip mask generation.…”

Section: History Of Inverse Lithographymentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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EUV mask synthesis with rigorous ILT for process window improvement

Cited by 2 publications

References 3 publications

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Full chip inverse lithography technology mask synthesis for advanced memory manufacturing

Inverse lithography technology: 30 years from concept to practical, full-chip reality

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